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1. 发明专利

JPH05128860A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH05128860A
公开(公告)日：1993-05-25
申请号：JP28651991
申请日：1991-10-31
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： YOKOYAMA YUJI , NAKAGAWA KAORU , AKIYAMA NOBORU , TANBA AKIHIRO , OTA TATSUYUKI
IPC分类号： G11C11/409
摘要： PURPOSE:To perform the high speed action of an input buffer circuit by connecting a collector to the power and making an emitter potential into an output digital signal by using a bipolar transistor for the output step of the input buffer circuit. CONSTITUTION:The output step of an input buffer circuit is constituted of bipolar transistors (Tr)Q0 and a P-type FETM0. The collector of the TrQ0 and the source of the FETM0 are connected to a power Vcc. A power IDSO poured into the base of the TrQ0 is decided by a voltage VGSO between the gate sources of the FETM0. Since the VSGO is VGSO=VINO, the gate voltage is not changed by the action of the TrQ0. Therefore, a current IDSO poured into the base of the TrQ0 becomes large and a collector current ICO of the TrQ0 can be enlarged. As the result, the output capacity can be quickly charged, and the output potential can be fast changed from a '0' level to a '1' level. Then, the high speed action of the input buffer circuit is possible.

2. 发明专利

JPH0555481A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0555481A
公开(公告)日：1993-03-05
申请号：JP21690191
申请日：1991-08-28
申请人： HITACHI LTD
发明人： NAKAMURA MASAYUKI , MIWA HITOSHI , NAKAI KIYOSHI , OTA TATSUYUKI
IPC分类号： H01L27/06 , H01L21/8249
摘要： PURPOSE:To markedly improve the breakdown strength of an input protective circuit itself to surge voltage for preparation of the input protective circuit of a semiconductor device of BiCMOS structure. CONSTITUTION:The surface of a semiconductor substrate 1 with a p-type buried layer 7 is spread with a BiCMOS-constituting epitaxial layer. This layer includes a plurality of p-wells/n-wells, and an n-well 6 is formed inside one p-well 2 out of those so that its area may increase according as the epitaxial layer gets thinner. The top face of the well 6 is provided with an n diffusion layer 3 as the input part of an input protective circuit. The p-well 2 includes n diffusion layers 4, 5 which surround the n diffusion layer 3 within the same plane, and these n diffusion layers 4, 5 are connected to a source voltage terminal (Vss) and a second source voltage terminal (Vcc), respectively, to constitute the output part of the input protective circuit.

3. 发明专利

JPH02246151A RESISTANCE MEANS, LOGIC CIRCUIT, INPUT CIRCUIT, FUSE-BLOWING CIRCUIT, DRIVE CIRCUIT, POWER-SUPPLY CIRCUIT AND ELECTROSTATIC PROTECTIVE CIRCUIT; SEMICONDUCTOR STORAGE DEVICE CONTAINING THEM, AND ITS LAYOUT SYSTEM AND TEST SYSTEM 失效
公开(公告)号：JPH02246151A
公开(公告)日：1990-10-01
申请号：JP6584189
申请日：1989-03-20
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： YANAGISAWA KAZUMASA , OTA TATSUYUKI , UDAGAWA SATORU , ISHII KYOKO , MIWA HITOSHI , NOZOE ATSUSHI , NAKAMURA MASAYUKI , MATSUMOTO TETSUO , KINOSHITA YOSHITAKA , KITSUKAWA GORO , KOBAYASHI YUTAKA , OUCHI YOSHIAKI , TSUKADA AKIMI , WADA SHOJI , MIHASHI KAZUO
IPC分类号： G11C11/409 , G05F3/24 , G11C11/401 , G11C11/403 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/28 , G11C29/34 , G11C29/46 , G11C29/50 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L27/10 , H01L27/108
摘要： PURPOSE:To realize a high integration of a memory array and to reduce a signal- transfer delay time in a peripheral circuit by a method wherein the memory array of a semiconductor device is constituted fundamentally of a dynamic memory cell and its peripheral circuit is constituted fundamentally of a Bi-CMOS logic gate circuit. CONSTITUTION:This Bi-CMOS dynamic RAM is provided with 8 memory mats MAT0 to MAT7. Dynamic memory cells of 132X516 pieces, i.e., 68112 pieces, are arranged in a grid shape at intersecting points of word lines and complementary bit lines. The memory mats MAT0 to MAT7 are started selectively when a corresponding selection signal AS0L, AS0R, AS1L or AS1R is at a high level, and autonomously and independently executes a series of operations which are required to select a word line and a data line or to drive a sense amplifier. As a result, a selective operation of the Bi-CMOS dynamic RAM is simplified and is executed at high speed; a storage capacity of the memory mats can be formed as a unit by making use of the capacity as an expansion unit.

4. 发明专利

JPS61166066A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS61166066A
公开(公告)日：1986-07-26
申请号：JP569185
申请日：1985-01-18
申请人： HITACHI LTD
发明人： OTA TATSUYUKI
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108
摘要： PURPOSE:To inhibit the variation of the quantity of a reference signal stored in a capacitance element for deciding informations in a dummy cell, to prevent a malfunction and to improve electrical reliability by forming a dummy cell array at the central section of a memory cell array and electrically connecting conductive plates for a capacitance element for storing informations in the memory cell array and the capacitance element for deciding informations in the dummy cell array. CONSTITUTION:Conductive plates 10 are shaped to the main surface sections of semiconductor substrates 1 in forming regions for capacitance elements for storing informations and capacitance elements for deciding informations, and constitute the capacitance elements for storing informations in memory cells and the capacitance elements for deciding informations in dummy cells together with a semiconductor substrate 8 and a first insulating film. The conductive plates 10 are unified between adjacent memory cells, and constituted as common electrodes in memory cell arrays 2, and unified between adjacent dummy cells and constituted as common electrodes in dummy cell arrays 3. Opening sections are formed in MISFET forming regions, etc. for a clear in the conductive plates 10, and the conductive plates are united by the memory cell arrays 2 and the dummy cell arrays 3 and connected electrically.

5. 发明专利

JPH0567737A SEMICONDUCTOR DEVICE HAVING INPUT PROTECTIVE CIRCUIT AND MANUFACTURING METHOD THEREOF 失效
公开(公告)号：JPH0567737A
公开(公告)日：1993-03-19
申请号：JP22688791
申请日：1991-09-06
申请人： HITACHI LTD
发明人： NAKAMURA MASAYUKI , MIWA HITOSHI , NAKAI KIYOSHI , OTA TATSUYUKI , MIYAZAWA KAZUYUKI
IPC分类号： H01L27/06 , H01L21/8249
摘要： PURPOSE:To considerably enhance breakdown strength against a surge voltage in an input protective circuit itself when the input protection circuit in a semiconductor device having a BiCM0S structure is made. CONSTITUTION:On the semiconductor substrate surface formed with a p embedded layer 2, an epitaxial layer for constructing a BiCM0S is formed. A plurality of n well/p well regions are formed in this layer, and in one well 3 thereof, input protective circuits 10, 20 are provided. Under the well in which this input protective circuit is formed, the p embedded layer 2 is not formed, and namely the well comprising the epitaxial layer is directly formed on the substrate. An n diffusion layer is formed on the well 3 surface to be an input terminal of the input protective circuit, and the well 3 is connected to a power source voltage terminal (Vcc, Vss). When the p embedded layer 2 is formed, impurities are introduced based on a mask pattern corresponding to a region provided with the input protective circuit.

6. 发明专利

JPH04252494A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH04252494A
公开(公告)日：1992-09-08
申请号：JP2685591
申请日：1991-01-28
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： NAKAI KIYOSHI , MIWA HITOSHI , NAKAMURA MASAYUKI , OTA TATSUYUKI , MAEDA TOSHIO
IPC分类号： G11C11/413 , G11C11/409
摘要： PURPOSE:To improve the noise resistance in a complementary common data line and to improve the noise margin in a main amplifier. CONSTITUTION:The counter distance between the complementary common data line pair and the signal line adjacent to it is made equal between each pair lines by applying the twist structure interchanging the mutual arrangement alternately in the process to complementary common data line for read CDR1, CDR1*, CDR2, CDR2* and simultaneously arranging the shield wiring for earth potential SD1, SD2 while making them adjacent to the complementary common data line. The change of level caused by the noise from the adjacent signal line becomes equal each other between the pair signal lines in the complementary common data line. The logic value inversion is not performed for the read data transmitted to the complementary common data line undesiredly and is allowed to be amplified in a main amplifier MA including a bipolar transistor.

7. 发明专利

JPH0258798A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH0258798A
公开(公告)日：1990-02-27
申请号：JP20834188
申请日：1988-08-24
申请人： HITACHI LTD
发明人： OTA TATSUYUKI
IPC分类号： G11C29/00 , G11C11/401 , G11C29/42 , H01L27/10
摘要： PURPOSE:To obtain a low-cost dynamic RAM having an error correcting function by adding a 1-bit horizontal parity bit and vertical parity bit to the input and output data of the RAM. CONSTITUTION:This dynamic RAM is constituted in a memory which, for example, can simultaneously input or output 4-bit data and 1-bit horizontal parity bit is added to the 4-bit data. Therefore, the dynamic RAM is provided with four memory arrays MARY0 - MARY3 provided against the 4-bit data and another memory array MARYP provided against the horizontal parity bit. One-bit vertical parity bit is further added to the low-address of each memory array MARY0 - MARY3 and MARYP. When abnormality is simultaneously detected from the horizontal and vertical parity bits, the data read out of the corresponding memory array are selectively inverted. Therefore, a low-cost dynamic RAM having an error correcting function can be obtained.

8. 发明专利

JPS61218162A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS61218162A
公开(公告)日：1986-09-27
申请号：JP5833885
申请日：1985-03-25
申请人： HITACHI LTD
发明人： OTA TATSUYUKI
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/08 , H01L27/108
摘要： PURPOSE:To prevent a latchup phenomenon by forming a semiconductor region for connecting a reference voltage to an inner well region of the width size of an MISFET in a gate longitudinal direction, thereby stabilizing the potential of the well region. CONSTITUTION:A plurality of MISFETs are formed in a well region 2 formed on the main surface of a substrate 1, thereby forming, for example, a DRAM. Numeral 10a designates a reference voltage connecting semiconductor region which is formed on the main surface of the inner region 2 of the width size of the MISFET in a gate longitudinal direction. The region 10a is formed in a vacant space between semiconductor elements and particularly between a P-channel MISFET and an N-channel MISFET. The region 10a increases the number of connections with conductive layers applied with a reference voltage, and stably holds the prescribed potential at the region 2, thereby preventing a latchup phenomenon.

9. 发明专利

JPH05326821A CAPACITOR FORMING METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, CAPACITOR-ATTACHED LEAD FRAME, AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH05326821A
公开(公告)日：1993-12-10
申请号：JP12713192
申请日：1992-05-20
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： WADA SHOJI , YOSHIOKA HIROSHI , MIWA HITOSHI , NAKAMURA MASAYUKI , OTA TATSUYUKI
IPC分类号： H01L23/50 , H01L21/822 , H01L27/04
摘要： PURPOSE:To provide the technique with which a stabilized operational margin and reliability can be improved by a method wherein a large capacitor is formed in a power supply system without increasing chip area, and a low-resistance wiring is used. CONSTITUTION:Dielectrics 3 and 4 are laminated on a lead frame 1, capacitor is formed using the lead frame 1 as one of electrodes, and the electrode such as above-mentioned is used in a semiconductor chip 22. As a result, the formation of a high-capacitance capacitor in the semiconductor chip 22 is unnecessitated, and the node of the semiconductor chip 22 can be connected in low resistance by coupling the capacitor to the semiconductor chip 22 using a bonding wire.

10. 发明专利

JPH04258884A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH04258884A
公开(公告)日：1992-09-14
申请号：JP4095291
申请日：1991-02-12
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： OTA TATSUYUKI , MIWA HITOSHI , NAKAMURA MASAYUKI , WADA SHOJI , MIYAZAWA KAZUYUKI
IPC分类号： G11C11/407 , G11C11/409 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108 , H03K19/0175
摘要： PURPOSE:To make a system stable and reliable by limiting the amplitude of output signals of a data output buffer and suppressing noise induced by a Bi.CMOS dynamic RAM, etc., through a large fluctuation of a power source voltage. CONSTITUTION:A voltage limiter circuit VL contains MOSFETs Q11-Q13 which are arranged in series between the power source voltage VCC and the earth potential of the circuit. Among them, FET Q11 is constantly switched on as the gate is at the ground potential. FET Q11-Q13 turn to a diode form as the gate and drain is connected. The voltage of the commonly connected drain of FET Q1 and Q11 is supplied to the data output buffers DOB0-DOB3 as the output power source voltage VOL. Thus, when the absolute value of the voltage VCC is smaller than the resultant threshold value VTH of FET Q11-Q13, the output VOL is equal to the voltage VCC, and when VCC exceeds VTH, it is clamped at the potential of this resultant threshold value.

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