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1. 发明专利

JPH03228335A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH03228335A
公开(公告)日：1991-10-09
申请号：JP2200090
申请日：1990-02-02
申请人： HITACHI LTD , HITACHI DEVICE ENG , HITACHI VLSI ENG
发明人： SHIBA TAKEO , OGIWARA ITARU , TAMAOKI YOICHI , SHIMAMOTO HIROMI , KOBAYASHI TAKASHI , NANBA MITSUO
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8222 , H01L27/06 , H01L27/082 , H01L29/732
摘要： PURPOSE:To reduce the specific resistance and the parasitic resistance of a polycrystalline silicon electrode in a bipolar transistor by using polycrystalline silicon with a grain size above a specific value for the polycrystalline silicon electrode of base, emitter, or collector. CONSTITUTION:In a vertical bipolar transistor consisting of a conductivity-I first layer 2 provided in a semiconductor substrate 1, a conductivity-II second layer 7 provided on it, and a conductivity-I third layer 8 provided further on it, electrodes 5, 10 made of polycrystalline silicon film are connected to the first layer 2, second layer 7, or third layer 8, so that the largest side of its polycrystalline silicon grain is 1mum or larger. For example, amorphous silicon layers are deposited, injected with impurity atoms, and heat-treated at 900 deg.C or higher temperature, thus forming base electrodes 5 and emitter electrodes 10 consisting of polycrystalline silicon with a grain size of 2mu or larger. Thereafter, a passivation film 11 is deposited to form base, emitter, and collector metal electrodes 12, 14.

2. 发明专利

JP2001085540A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JP2001085540A
公开(公告)日：2001-03-30
申请号：JP25626699
申请日：1999-09-09
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： KURATA HIDEAKI , KOBAYASHI TAKASHI , KOBAYASHI NAOKI , KUME HITOSHI , KIMURA KATSUTAKA , SAEKI SHUNICHI
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To reduce defect density of a semiconductor integrated device which has a 3rd gate, while making the device fine and improving its operating speed. SOLUTION: This integrated circuit device has a source-drain diffused layer region 205 of a 2nd conductivity-type formed in a well 201 of a 1st conductivity type, a floating gate 203b formed on the semiconductor substrate 200 across an insulating film 202, a control gate 211a which is formed on the floating gate 203b across a silicon oxide film 210, and a 3rd gate 207a which is formed across the semiconductor substrate, the floating gate, the control gate, and an insulating film and different from the floating gate and control gate. In this case, the 3rd gate is embedded in the gap of the floating gate perpendicular to word lines and channels and insulating films 206a on both its end surfaces are different in film thickness.

3. 发明专利

JP2001085541A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JP2001085541A
公开(公告)日：2001-03-30
申请号：JP25799099
申请日：1999-09-10
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： KOBAYASHI TAKASHI , GOTO YASUSHI , KURE TOKUO , KURATA HIDEAKI , KUME HITOSHI , KIMURA KATSUTAKA , SAEKI SHUNICHI
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To improve the reliability of a semiconductor integrated circuit with a 3rd gate after repetitive writing, while making the device fine and improving its operating speed. SOLUTION: This integrated circuit device has a source-drain diffused layer region 205 of a 2nd conduction type formed in a well 201 of a 1st conductivity- type, a floating gate 203b formed on a semiconductor substrate 200 across an insulating film 202, a control gate 211a formed on the floating gate 203b across a silicon oxide film 210a into which nitrogen is introduced, and the 3rd gate 207a which is formed across the semiconductor substrate, the floating gate, the control gate, and an insulating film and different from the floating gate and control gate. In this case, the 3rd gate is embedded in the gap of the floating gate perpendicular to word lines and channels, at a altitude lower than the floating gate 203b.

4. 发明专利

JPH08181231A NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH08181231A
公开(公告)日：1996-07-12
申请号：JP32441494
申请日：1994-12-27
申请人： HITACHI LTD , HITACHI VLSI ENG , HITACHI DEVICE ENG
发明人： ADACHI TETSUO , KATO MASATAKA , KOBAYASHI TAKASHI , MORIMOTO TADAO , MIYAMOTO NAOKI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE: To provide a nonvolatile semiconductor storage device, in which charge holding characteristics are improved and which has high reliability, and manufacture thereof. CONSTITUTION: In a nonvolatile semiconductor storage device with a floating gate electrode 4 formed on a semiconductor substrate 1 through a gate insulating film 3 and a control gate electrode 6 formed onto the upper section of the gate electrode 4 through an inter-layer insulating film 5, a process, in which the floating gate electrode is shaped, a process in which the upper end sections of the floating gate electrode are rounded, and a process in which the inter-layer insulating film is formed, are contained. Accordingly, field concentration in the inter-layer insulating film can be prevented and isolation voltage and distubance resistance are not lowered by forming the upper end sections of the floating gate electrode in an arcuate shape, thus thinning the inter-layer insulating film, then realizing the large nonvolatile semiconductor storage device.

5. 发明专利

JP2001126490A WRITE-IN METHOD FOR NON-VOLATILE SEMICONDUCTOR MULTI- LEVEL MEMORY 失效
公开(公告)号：JP2001126490A
公开(公告)日：2001-05-11
申请号：JP30183199
申请日：1999-10-25
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： KOBAYASHI NAOKI , KURATA HIDEAKI , KIMURA KATSUTAKA , KOBAYASHI TAKASHI , SAEKI SHUNICHI
IPC分类号： G11C16/02 , G11C11/56 , G11C16/00 , G11C16/04 , G11C16/06
摘要： PROBLEM TO BE SOLVED: To realize high speed write-in and high reliability in a non-volatile multi-level memory. SOLUTION: In a non-volatile semiconductor memory in which information of a multi-level is stored in one memory cell by setting plural threshold values, write-in (write-n 1) for a threshold value being the farthest from an erasing state is performed previous to write-in for the other threshold value, write-in for the other threshold value is performed successively from data having a value being near an erasion state, also, at the time of write-in of each case, write-in is performed simultaneously for a cell in which data of a threshold value being far from an erasion state (write-in 2, write-in 3).

6. 发明专利

JP2001067884A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JP2001067884A
公开(公告)日：2001-03-16
申请号：JP24632799
申请日：1999-08-31
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： KURATA HIDEAKI , KOBAYASHI NAOKI , KOBAYASHI TAKASHI , KIMURA KATSUTAKA , KUME HITOSHI , SAEKI SHUNICHI
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C16/06 , G11C16/34
摘要： PROBLEM TO BE SOLVED: To realize a high write throughput by repeating a write verify operation until writing to all memory cells corresponding to a data level of a predetermined number finishes. SOLUTION: A write bias is applied to write to a memory cell 1 which stores data of 2 bits per cell. Subsequently, the cell is verified with the use of data of a data hold circuit 6. A corresponding judge circuit 4 is first activated by selecting the memory cell 1 having a write target of a first state. Then, a word line WL of the memory cell is set to a first state verify level, and the verified result of the first state is held into the judge circuit 4 corresponding to the first state write memory cell 1. Connecting a bit line BL to the judge circuit 4 is carried out with the use of data of the data hold circuit 4. When the verified results from the first state through the third state are all obtained, batch judgment is carried out before writing to an insufficiently written memory cell.

7. 发明专利

JP2001028428A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND MANUFACTURE AND OPERATION THEREOF 失效
公开(公告)号：JP2001028428A
公开(公告)日：2001-01-30
申请号：JP20024299
申请日：1999-07-14
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： KOBAYASHI TAKASHI , KURATA HIDEAKI , KOBAYASHI NAOKI , KUME HITOSHI , KIMURA KATSUTAKA , SAEKI SHUNICHI
IPC分类号： G11C16/04 , H01L21/822 , H01L21/8247 , H01L27/04 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To aim at miniaturization of a semiconductor integrated circuit device and the speeding up of the operating speed of the device and also to aim at reduction in the defect density in insulating films in the device having third gates. SOLUTION: A semiconductor circuit device has a first conductivity-type well 101 formed in a semiconductor substrate 100, second conductivity type source/drain diffused layer regions 105 in a well 101, floating gates 103b formed on the substrate 100 via an insulating film 102, control gates 111a formed via each gate 103b and an insulating film 110a, a word line formed by connecting the gates 111a with each other and third gates 107a which are formed via the substrate 100, the gates 103b, the gates 111a and the film 110a and are different from the gates 103b and the gates 111a. In this case, the above gates 107a are arranged, in such a way that the gates 107a are embedded and exist in the gaps between the gates 103b existing in the directions vertical to the word line and a channel.

8. 发明专利

JPH06260303A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH06260303A
公开(公告)日：1994-09-16
申请号：JP4773093
申请日：1993-03-09
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： SHIMAMOTO HIROMI , UCHINO TAKASHI , SHIBA TAKEO , ONISHI KAZUHIRO , TAMAOKI YOICHI , KOBAYASHI TAKASHI , KIKUCHI TOSHIYUKI , IKEDA TAKAHIDE
IPC分类号： H01C7/06 , H01L21/02 , H01L21/822 , H01L27/04 , H01L27/06
摘要： PURPOSE:To provide a polycrystalline silicon resistor element, whose resistance- value dispersion is small and temperature dependency with respect to an arbitrary resistance value is less, and the manufacturing method thereof. CONSTITUTION:This device comprises the double-layer structure of a first polycrystalline silicon layer (3b) having the large particle diameter and a second polycrystalline silicon layer (3a) having the small particle diameter. The polycrystalline silicon layers having the mutually reverse resistance-temperature characteristics are used as the resistor elements. The polycrystalline silicon layer having the large particle diameter is formed by the high dose ion implanting method.

9. 发明专利

JP2012244109A Non-volatile storage 审中-公开
标题翻译：非挥发性储存
公开(公告)号：JP2012244109A
公开(公告)日：2012-12-10
申请号：JP2011115887
申请日：2011-05-24
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KINOSHITA KATSUJI , SASAKO YOSHITAKA , KOBAYASHI TAKASHI
IPC分类号： H01L27/105 , G11C13/00 , H01L27/10 , H01L45/00
摘要： PROBLEM TO BE SOLVED: To provide a non-volatile storage having high density and high reliability.SOLUTION: A non-volatile storage comprising a laminated body having interlayer dielectrics 11 to 15 alternately laminated on a word line 2 extending along a main surface of a substrate and gate polysilicon layers 21p to 24p: a bit line 3 formed on the laminated body and extending in a direction orthogonal to the word line 2; and a polysilicon diode PD provided at cross points of the word line 2 and the bit line 3, is manufactured. A gate insulating film 9, channel silicon films 8a, 8b and a resistance change material layer 7 are provided in the order from an internal wall of a connection hole for passing through the laminated body and exposing an upper surface of the polysilicon diode PD. The word line 2 and the bit line 3 are electrically connected with each other via the polysilicon diode PD, and the channel silicon films 8a, 8b, and a total film thickness of the channel silicon films 8a, 8b in a direction orthogonal to the internal wall is defined as a film thickness capable of depleting the channel silicon films 8a, 8b.
摘要翻译：要解决的问题：提供具有高密度和高可靠性的非易失性存储器。解决方案：一种非易失性存储器，包括层叠体，层叠体层叠在沿着基板的主表面延伸的字线2上的层间电介质层11〜15，栅极多晶硅层21p〜24p：形成在基板2上的位线3 层叠体并且在与字线2正交的方向上延伸; 并且制造设置在字线2和位线3的交叉点处的多晶硅二极管PD。从用于通过层叠体的连接孔的内壁起依次设置栅极绝缘膜9，沟道硅膜8a，8b和电阻变化材料层7，并露出多晶硅二极管PD的上表面。字线2和位线3经由多晶硅二极管PD和沟道硅膜8a，8b彼此电连接，并且沟道硅膜8a，8b在与内部正交的方向上的总膜厚度壁被定义为能够耗尽沟道硅膜8a，8b的膜厚度。版权所有（C）2013，JPO＆INPIT

10. 发明专利

JP2012228126A Digital type protective relay device 有权
标题翻译：数字式保护继电器
公开(公告)号：JP2012228126A
公开(公告)日：2012-11-15
申请号：JP2011095604
申请日：2011-04-22
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KOBAYASHI TAKASHI
IPC分类号： H02H3/05 , H02H3/02
摘要： PROBLEM TO BE SOLVED: To provide a digital type protective relay device 1 which, while continuing its protective relay operation, detects a fault and a characteristic change in an input conversion unit 2 and an analog/digital conversion unit 3, and also to reduce workload during periodic inspection.SOLUTION: A digital type protective relay device 1 comprises: an inspection signal generation unit 8 which supplies a prescribed inspection signal to each unit; a transformer 23, in an input conversion unit 2, which has a second winding on the primary side to which an inspection signal is input; and signal synthesis circuits 34, 35 and 36 which superpose an inspection signal on respective input signals per input channel to an analog filter 31, a multiplexer 32 and an A/D converter 33. An arithmetic processing unit 4, during automatic inspection, detects, while continuing to execute protective relay arithmetic, a fault and characteristic degradation per input channel in each of the units by using an inspection signal component at prescribed higher order frequency; during periodic inspection, it feeds an inspection signal at plural frequencies including the fundamental wave into the input conversion unit 2, thereby measuring the input characteristics of the device as a protective relay.
摘要翻译：要解决的问题：提供一种数字式保护继电器1，其在继续保护继电器操作的同时检测输入转换单元2和模拟/数字转换单元3中的故障和特性变化，并且还以定期检查减少工作量。数字式保护继电器1包括：检查信号生成单元8，其向每个单元提供规定的检查信号; 变压器23，在输入转换单元2中，在输入检查信号的初级侧具有第二绕组; 以及信号合成电路34,35和36，其将每个输入信道的相应输入信号上的检查信号叠加到模拟滤波器31，多路复用器32和A / D转换器33.运算处理单元4在自动检查期间，同时通过使用规定的高阶频率的检查信号分量继续执行保护继电器运算，每个输入通道的故障和特性劣化; 在定期检查期间，将包括基波的多个频率的检查信号馈送到输入转换单元2，从而测量作为保护继电器的装置的输入特性。版权所有（C）2013，JPO＆INPIT

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