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1. 发明专利

JPS63293789A BIPOLAR TYPE RAM 失效
公开(公告)号：JPS63293789A
公开(公告)日：1988-11-30
申请号：JP12819787
申请日：1987-05-27
申请人： HITACHI LTD
发明人： USAMI MASAMI , AKIMOTO KAZUYASU , UCHIYAMA TAKEO , IWABUCHI MASATO
IPC分类号： G11C11/414 , G11C11/34
摘要： PURPOSE:To speed up the operation of the titled RAM while suppressing the increment of power consumption or its area by providing a differential change- over switch circuit for alternatively outputting the output signals of plural sense amplifiers to the output parts of the sense amplifiers. CONSTITUTION:The differential change-over switch circuit (RSW) is provided on the output parts of two sense amplifiers SA0, SA1. The switch circuit RSW selectively outputs output signals from sense amplifiers SA0, SA1 in accordance with the level of selecting signals, the inverse of OEA, the inverse of OEB. A data output buffer DOB forms a reading output signal for amplifying the signal selectively outputted from the sense amplifier SA0 or SA1 through the switch RSW and sending the amplified signal to an external terminal I/O. Consequently, the output circuit can be used in common, and while suppressing the increment of the area or power consumption, the speed-up of operation can be attained.

2. 发明专利

JPS60187048A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60187048A
公开(公告)日：1985-09-24
申请号：JP4201884
申请日：1984-03-07
申请人： HITACHI LTD
发明人： UCHIYAMA TAKEO , NAKANO TETSUO , UCHIDA AKIHISA , MITAMURA ICHIROU
IPC分类号： H01L27/04 , H01L21/76 , H01L21/822 , H01L21/8222 , H01L27/082
摘要： PURPOSE:To enable to constitute a capacitor of relatively large capacity without increasing the size of a chip by a method wherein the junction capacitance between a substrate and the buried layer of conductive type different from that of the substrate is properly utilized. CONSTITUTION:An N buried layer 2 is partially formed on a P type semiconductor substrate 1, and an N epitaxial layer 3 is formed thereon. Then, a U- groove is formed in such a manner that it penetrates the layers 2 and 3, and an insulating film 5 is formed inside the U-groove, and a U-groove isolation region 8 is provided by filling poly silicon in the U-groove. Also, an N region 11 to be turned to the pulling-up hole of the layer 2 is formed at one end of the layer 2, and a P region 10 to be turned to the pulling-up hole of the substrate 1 surrounded by the region 8 is formed at an arbitrary position on the substrate 1 which is separated a little from the layer 2. Electrodes 4a and 4b are formed on pulling-up holes 10 and 11, and the junction capacitance which is parasitic between the layer 2 and the substrate 1 is properly utilized as the bypass capacitor of an internal source circuit. As a result, the bypass capacitor can be constituted without increasing the chip size.

3. 发明专利

JPS63308789A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS63308789A
公开(公告)日：1988-12-16
申请号：JP14306387
申请日：1987-06-10
申请人： HITACHI LTD
发明人： USAMI MASAMI , AKIMOTO KAZUYASU , UCHIYAMA TAKEO , IWABUCHI MASATO
IPC分类号： G11C11/414 , G11C7/22 , G11C11/416
摘要： PURPOSE:To optimize the relation of time between a start control signal and a write pulse by providing a timing generating circuit generating a write pulse satisfying a prescribed timing condition under a start control signal supplied externally. CONSTITUTION:A write enable signal, the inverse of WE is fed to a timing generating circuit TG in the same timing as the address signal and an input write data. A strobe signal is generated with a slight delay to chip select signal, the inverse of CS, the strobe signal is used as a trigger signal and a latch FF1 is set or reset selectively according to the signal, the inverse of WE. Moreover, the write pulse phiw is formed selectively while keeping a prescribed time with the signal, the inverse of CS according to the state of the latch FF1. The relation of time is optimized so that the memory cycle of the bipolar RAM is the highest. Thus, the timing condition with respect to the signal, the inverse of WE of the bipolar RAM is relaxed and the memory cycle is quickened.

4. 发明专利

JPS6043293A MEMORY WITH LATCH 失效
公开(公告)号：JPS6043293A
公开(公告)日：1985-03-07
申请号：JP15014383
申请日：1983-08-19
申请人： HITACHI LTD
发明人： KITSUKAWA GOROU , UCHIYAMA TAKEO , MITAMURA ICHIROU
IPC分类号： G11C11/413 , G11C7/00 , G11C11/34 , G11C11/409
摘要： PURPOSE:To prevent an output latch circuit from oscillating owing to a sense signal from an indeterminate memory cell right after writing or malfunction because of noise induction by suppressing a strobe signal for output latching in LSI in a write cycle where an output need not be determined in a semiconductor memory. CONSTITUTION:A gate circuit 24 is provided to control a clock signal CLOCK-B for output latching, and a clock enable signal CLE is supplied externally to control the gate circuit 24; and a latch strobe signal VCLK is impressed normally to the output latch circuit in a read cycle, and inhibited from inverting the output latch circuit in a write cycle. An actual circuit shifts the clock enable signal CLE in level by one stage through an emitter follower circuit and then shifts it to the lower-stage level of a series gate circuit, inputting the result to the lower stage of the series gate circuit. When input CLE is at a high level, VCLK is in a state Lowfix regardless of CLOCK-B and VCLK does not inverts the output latch circuit.

5. 发明专利

JPS57164499A TESTING METHOD OF IC MEMORY 失效
公开(公告)号：JPS57164499A
公开(公告)日：1982-10-09
申请号：JP4932481
申请日：1981-04-03
申请人： HITACHI LTD
发明人： UCHIYAMA TAKEO
IPC分类号： G11C29/00 , G01R31/28 , G11C29/50 , G11C29/56
摘要： PURPOSE:To quickly select an IC memory which is weak against alpha rays under non-destructive condition, by inserting an inhibiting cycle between the write cycle and the readout cycle, and setting supply voltage of the IC memory in the cycle to a low level. CONSTITUTION:The supply voltage is set to, for example, +V0, the power source is turned on, and the write cycle is started. In this write cycle, the test pattern is written in an IC memory. When the writing is completed, the supply voltage is dropped to +V2, and the inhibting cycle is started. As to the voltage value V0, it is usually selected to considerably lower value than +V0-10%. Afterward, the supply voltage is raised to +V0, information stored in the IC memory is read ot by starting the readout cycle, and the normality is judged by comparing the readout information with the written test pattern. Then, similar test sequence is executed on the inverse test pattern.

6. 发明专利

JPS5658249A PACKAGE FOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS5658249A
公开(公告)日：1981-05-21
申请号：JP13417679
申请日：1979-10-19
申请人： HITACHI LTD
发明人： UCHIYAMA TAKEO
IPC分类号： H01L23/29 , H01L23/31 , H01L23/556
摘要： PURPOSE:To shield alpha rays generated from the inner wall of a package by filling a hollow generated therein with a resin such as plastics when an IC chip is housed in the package made of a ceramic. CONSTITUTION:The IC chip 5 is housed in a recess of the ceramic package 1 which is provided with a plurality of external connection lead wires 3 facing downward. A specified connection is made with a bonding wire 4 and the open end of the top thereof is covered with a metal cap 2. Thus, the IC package is constructed. The hollow herein produced in the package 1 is filled with a resin 6 such as plastics. This enables complete shieling of alpha rays as emitted from the ceramic inner wall thereby improving the heat dissipating effect with a less heat resistance.

7. 发明专利

JPS6381685A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS6381685A
公开(公告)日：1988-04-12
申请号：JP22595286
申请日：1986-09-26
申请人： HITACHI LTD
发明人： AKIMOTO KAZUYASU , USAMI MASAMI , UCHIYAMA TAKEO
IPC分类号： G11C11/414 , G11C11/34
摘要： PURPOSE:To diminish the occurrence of a defective function even when an address signal is switched at high speed by providing a circuit which makes an auxiliary read-out current flow for a time after a digit line is switched at the time of the selection of the digit line. CONSTITUTION:In control circuits CSC1, CSC2, when the output of a Y driver Y-RD changes to an H level, a current flows in transistors (Tr)Q12, Q22, and TrsQ13, Q23 come to ON. Then, TrsQ11, Q21 for drawing a charge come to ON, and being caused by this, the auxiliary current DELTAIR flows from a digit lines D, the inverse of D. Therefore, a memory cell MC, being selected at that time, is attracted by a current, which is a read current IR, due to a constant current source I2, I3 and added with the current DELTAIR. Besides, capacitors C1, C2 are connected in parallel with resistors R12, R22 in the circuits CSC1, CSC2. These capacitors C1, C2 act as speed-up capacitors, and when the output signal of a driver Y-DR changes to the H level, they make the build-up of the current DELTAIR fast, therefore, a memory cell margin is improved.

8. 发明专利

JPS6045996A BIPOLAR TYPE RANDOM ACCESS MEMORY 失效
公开(公告)号：JPS6045996A
公开(公告)日：1985-03-12
申请号：JP15155183
申请日：1983-08-22
申请人： HITACHI LTD
发明人： UCHIYAMA TAKEO , MITAMURA ICHIROU , KITSUKAWA GOROU
IPC分类号： G11C11/414 , G11C11/34 , H01L21/8229 , H01L27/10 , H01L27/102
摘要： PURPOSE:To expand the operation margine of a bipolar type RAM by switching a reading reference voltage in accordance with the number of memory cells to be read out. CONSTITUTION:When an operation mode control signal FS is in the low level and only one memory cell constituted by transistors (TRs) Q4, Q5 forming an FF by the cross coupling of word lines WO is to be read out, differential TRs Q1, Q2 in a current switching circuit are turned on and off respectively. consequently, constant current I1 does not flow into a resistor R1 and the readout reference voltage is determined by constant current IO flowing into the resistors R1, R2. When the signal FS is turned to the high level to read out many memory cells simultaneously, the constant current I1 also flows into the resitor R1 and the reading reference voltage is dropped. The same rule is applied also to other word lines and the simultaneous reading of plural blocks reduces the reference voltage as compared to the memory reading of one block, so that the level margine of the holding voltage of the memory cells is prevented from deterioration and the operation margine of the bipolar type RAM can be expanded.

9. 发明专利

JPS6045992A BIPOLAR TYPE RANDOM ACCESS MEMORY 失效
公开(公告)号：JPS6045992A
公开(公告)日：1985-03-12
申请号：JP15155083
申请日：1983-08-22
申请人： HITACHI LTD
发明人： UCHIYAMA TAKEO , MITAMURA ICHIROU , KITSUKAWA GOROU
IPC分类号： G11C7/00
摘要： PURPOSE:To expand the operation margine of a bipolar type RAM by switching the selecting level of a word line in accordance with the number of memory cells to be read out. CONSTITUTION:When an operation mode control signal FS is turned to the low level to read out one memory cell constituted of transistors (TRs) 5, 6, etc. forming an FF, a TRQ11 for differential amplifier in a current switching circuit is turned off and a TRQ12 to which a reference voltage VS is impressed at its base is turned on. Consequently, constant current I flows into a resistor R1 and the selecting voltage of a word line WO reaches a prescribed value. When the signal FS is turned to the high level to read out many memory cells, the constant current does not flow into the resistor R1 and voltage drop is not generated, so that the selecting voltage of the word line WO is increased. The same rule is also applied to other word lines and the selecting voltage of word lines at the reading out many memory blocks is higher than the memory reading of one block, so that the operation margine of the bipolar type RAM is expanded.

10. 发明专利

JPS5427327A TEST CIRCUIT FOR MEMORY 失效
公开(公告)号：JPS5427327A
公开(公告)日：1979-03-01
申请号：JP9137277
申请日：1977-08-01
申请人： HITACHI LTD
发明人： UCHIYAMA TAKEO
IPC分类号： G11C29/00 , G06F11/22 , G11C29/56
摘要： PURPOSE:To secure an easy detection even for the bit which is easily affected by the noise, by changing the address signals to be applied to the memory to be tested into the plural series and comparing the data read out based on the address signal of one series with the data read out normally.

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