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1. 发明专利

JP2003264939A POWER UNIT AND INFORMATION PROCESSING SYSTEM USING IT 审中-公开
公开(公告)号：JP2003264939A
公开(公告)日：2003-09-19
申请号：JP2002063061
申请日：2002-03-08
申请人： HITACHI LTD
发明人： OKADA HIDEKI , HIDA YASUHIRO , AKIMOTO KAZUYASU , FUNATSU JUNICHI
IPC分类号： G06F1/26 , H02J9/00 , H02J9/06 , H02M3/00
摘要： PROBLEM TO BE SOLVED: To enlarge mounting space within a rack cabinet by the reduction of uninterruptive power units, and make a power unit have reliability equal to the uninterruptive power unit. SOLUTION: In this power unit, a plurality of modules, each of which has an AC/DC converter for converting AC input into DC power, a DC output battery, and a switch for selecting and outputting either the output of the above AC/DC converter or the output of the battery, are mounted. The DC output from the above power unit is supplied directly into a system device. COPYRIGHT: (C)2003,JPO

2. 发明专利

JPH1012333A MEMORY MOUNTING SYSTEM 失效
公开(公告)号：JPH1012333A
公开(公告)日：1998-01-16
申请号：JP16256296
申请日：1996-06-24
申请人： HITACHI LTD
发明人： SAKAKIBARA SHUNICHIRO , MOCHIDA TETSUYA , AKIMOTO KAZUYASU
IPC分类号： G11C5/00 , H01R23/68
摘要： PROBLEM TO BE SOLVED: To effectively mount memory modules of their different thickness dimension. SOLUTION: This mounting system arranges in a thickness direction and mount at least one of memory modules 70 and 80 with their whole thickness dimension a and thickness dimension b due to a difference in thickness of memory packages 72 and 82 to be mounted on module substrates 71 and 81 on a memory module socket 6. In this case, a width dimension c and an adjacent gap d of the memory module socket 60 where the memory modules 70 and 80 are inserted and removed is set to meet a condition of a

3. 发明专利

JPH02187992A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH02187992A
公开(公告)日：1990-07-24
申请号：JP728189
申请日：1989-01-16
申请人： HITACHI LTD
发明人： AKIMOTO KAZUYASU
IPC分类号： G11C11/413 , H01L27/10
摘要： PURPOSE:To contrive to allow a system to have a high performance by allowing an address driving circuit to have a latch function for fetching and holding the result of decoding of an address signal. CONSTITUTION:An X address driving circuit XD and a Y address driving circuit YD have a holding function of an address signal of a bipolar type RAM, and X and Y address buffers XAB, YAB have no latch function. The circuits XD, YD are provided with plural unit circuits provided in accordance with a word line or a complementary data line of a memory array MARY, and contain a latch for inputting and holding output signals of X and Y address decoders XAD, YAD, respectively. Latches provided on each unit circuit to the circuits XD, YD constitute a flip-flop circuit with a multi-input NOR function together with the corresponding unit circuit of the decoder XAD or YAD. In such a way, by deleting a decoding processing time and a transfer delay time of a signal wiring, etc., from a transfer delay time until a selecting signal is secured after a start control signal becomes effective, it can be realized to allow a digital system to have a high performance.

4. 发明专利

JPH0258796A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0258796A
公开(公告)日：1990-02-27
申请号：JP20833788
申请日：1988-08-24
申请人： HITACHI LTD
发明人： KOKUBU HISANORI , AKIMOTO KAZUYASU
IPC分类号： G11C11/414
摘要： PURPOSE:To improve the readout operating speed of a bipolar type RAM and operating speed of a memory with a logical function by arranging sense amplifiers, etc., which convert sense currents into voltage signals closely to corresponding data buffers, a logic circuit, etc. CONSTITUTION:Sense amplifiers SA0-SAn are arranged as close as possible to corresponding data buffers DB0-DBn and a logic circuit LC unconsciously of the distances to a memory array MARY. Therefore, a relatively long distance becomes necessary between a readout circuit and the sense amplifier SA0 and, even when a relatively large distribution resistance RS and floating capacity CS are coupled, the transmission delaying time of a readout signal and fluctuation of the delaying time can be reduced. Accordingly, the readout operating speed of a bipolar type RAM, etc., and the operating speed of a memory with a logical function can be increased.

5. 发明专利

JPH01187849A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH01187849A
公开(公告)日：1989-07-27
申请号：JP1065188
申请日：1988-01-22
申请人： HITACHI LTD
发明人： KOKUBU HISANORI , AKIMOTO KAZUYASU , USAMI MASAMI , HAGIUE KATSUMI , KAWASHIMA SEIICHI
IPC分类号： H01L21/822 , G05F3/22 , G11C11/401 , H01L21/82 , H01L27/04
摘要： PURPOSE:To prevent the input signal of an input circuit and a reference voltage or the like from varying due to a noise generated in the switching operation of an output circuit by providing the output circuit formed of wirings in which power supply lines are independent. CONSTITUTION:Power source lines for supplying a voltage which becomes a reference for forming an output signal in output selectors SELO1 and SELO2 as an output circuit of a semiconductor integrated circuit device LSI are Vcc1 composed of independent wirings distinguished from the power source lines Vcc2 of input circuits INC1-INC4 and other internal circuit. A reference voltage VBB as the logic threshold voltage of an ECL circuit and a constant voltage Vcs necessary to operate a constant-current source are respectively supplied from voltage generators VG11, VG12 and VG21, VG22 corresponding to the output circuits SELO1, SELO2 the input circuits INC1-INC4, and a constant- voltage generator VCG outputs a constant-voltage Vcs having substantially no temperature dependency and no power source dependency from the emitter of an output transistor Q7.

6. 发明专利

JPS6466961A INTEGRATED CIRCUIT 失效
公开(公告)号：JPS6466961A
公开(公告)日：1989-03-13
申请号：JP22357787
申请日：1987-09-07
申请人： HITACHI LTD
发明人： UCHIYAMA TAKEO , MITSUMOTO KINYA , AKIMOTO KAZUYASU , ISOMURA SATORU
IPC分类号： G05F3/16 , H01L21/66 , H01L21/822 , H01L21/8222 , H01L27/04 , H01L27/06
摘要： PURPOSE:To inhibit power consumption at a time when a device in which a plurality of LSIs are loaded onto the same substrate is tested, and to reduce a calorific value by separating a grounding terminal for a reference-voltage generating section in an internal power circuit from grounding terminals in other sections and connecting the grounding terminal for the reference-voltage generating section to a common external terminal for control combining a power supply. CONSTITUTION:Grounding terminals GND1 for reference-voltage generating sections 1 in internal power circuits 10 are isolated from grounding terminals for emitter followers 2, and the grounding terminals for the emitter followers 2 are connected in common with grounding terminals GND2 for load circuits B1-Bn. The grounding terminals GND1 for each internal power circuit 10 are connected in common with grounding line L1 and the grounding terminals GND2 with grounding line L2 respectively in response to each circuit in an LSI 20. Ground potential is applied to an external terminal 22, an output circuit 11 is brought to the state of operation, and currents cannot be flowed through the greater part of circuits only by controlling an external terminal 21.

7. 发明专利

JPS63268183A SEMICONDUCTOR MEMORY SYSTEM 失效
公开(公告)号：JPS63268183A
公开(公告)日：1988-11-04
申请号：JP9978687
申请日：1987-04-24
申请人： HITACHI LTD
发明人： AKIMOTO KAZUYASU , OGIUE KATSUMI , UCHIYAMA TAKEO
IPC分类号： G11C11/41 , G11C11/34 , G11C11/413 , G11C11/414
摘要： PURPOSE:To speed up the operation of the titled system by disposing logical parts around a memory circuit, packaging them on the same semiconductor chip, and making signals between circuits complementary signals that complement each other. CONSTITUTION:The logic parts LOG1, 2 are provided in front of and to the rear of a RAM, and respective circuit blocks are formed on the same one piece of semiconductor chip ICCHIP. In the LOG1, only an input buffer IB that forms a signal of low amplitude is provided, and no output buffers are provided. An address signal supplied from the LOG1 to the RAM and a data signal supplied from the RAM to the LOG2 are complementary signals respectively. Accordingly, the amplitude of a signal can be made lower in comparison to a case where a signal is transmitted/received through one piece of signal line. As a result, the shifting of signals come swifter and the delay time of the entire circuit also is made shorter, thus the operating speed of the system is improved. Furthermore, the complementary signal has a double margin against noise.

8. 发明专利

JPS60171758A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS60171758A
公开(公告)日：1985-09-05
申请号：JP2701284
申请日：1984-02-17
申请人： HITACHI LTD
发明人： NAKANO TETSUO , MITAMURA ICHIROU , AKIMOTO KAZUYASU , IWABUCHI MASATO
IPC分类号： H01L27/04 , H01L21/331 , H01L21/822 , H01L21/8222 , H01L27/02 , H01L27/082 , H01L29/73 , H01L29/732
摘要： PURPOSE:To contrive to improve the electrostatic breakdown withstand voltage of a semiconductor integrated circuit device by a method wherein the built-in pull-down resistor set at a comparatively high-resistance value in a degree that the resistance does not affect the output level of the output transistor is connected to the emitter of the output transistor of an open-emitter constitution. CONSTITUTION:An output transistor Q3 of an open-emitter constitution has an emitter connected to the external terminal. A pull-down resistor R2 of a comparatively high-resistance value in a degree that the resistance does not substantially affect the output level of the transistor Q3 is connected between the emitter of the transistor Q3 and the power terminal Vee on the negative side. For example, a P type diffusion region 5 formed at the same time at a time when impurities are diffused in the base of the transistor Q3 is utilized as the resistor R2 on the surface of an element forming region 4 surrounded with insulator isolated regions 3. By this way, when negative static electricity generates in an output terminal OUT, discharge current (-i) runs through the resistor R2 and even though positive static electricity generates in the output terminal OUT, discharge current runs through the resistor R2. As a result, an electrostatic breakdown of the output transistor Q3 can be prevented.

9. 发明专利

JPS59229783A BIPOLAR RAM 失效
公开(公告)号：JPS59229783A
公开(公告)日：1984-12-24
申请号：JP10256883
申请日：1983-06-10
申请人： HITACHI LTD
发明人： AKIMOTO KAZUYASU , NAKANO TETSUO , KATOU YUKIO
IPC分类号： G11C11/414 , G11C11/34
摘要： PURPOSE:To attain switching between an alternative current and a 1/2 current approximately equal to said alternative current which are supplied to a pair of output transistors with a simple circuit, by adding a function to an input data buffer to deliver a fixed intermediate level through a read-out operation. CONSTITUTION:In a writing mode of a terminal WE at a low level, a constant current I is flowed alternatively only to the side of an output transistor (TR) that produces output voltage V1 or V2 of a low level in an ON/OFF mode of a differential TR Q31 or Q30. A data input buffer DIB turns on a TRQ11 with a high level of the terminal WE to supply a constant current to resistances R4 and R5 by 1/2 respectively and fixes the output level at an intermediate level regardless of the signal supplied from an external terminal Din. The current I flows to the TRs Q30 and Q31 by 1/2 owing to the intermediate level of the output of the buffer DIB. Thus the reference voltage Vref can be obtained.

10. 发明专利

JPH10327133A SIMULTANEOUS TWO-WAY TRANSMISSION SYSTEM 失效
公开(公告)号：JPH10327133A
公开(公告)日：1998-12-08
申请号：JP13662997
申请日：1997-05-27
申请人： HITACHI LTD
发明人： GOTO TSUTOMU , ISHIBASHI KENICHI , HAYASHI TAKEHISA , YAMAGIWA AKIRA , AKIMOTO KAZUYASU
IPC分类号： H03K19/0175 , H04L5/14
摘要： PROBLEM TO BE SOLVED: To ensure a noise margin even when a power supply voltage of an input output circuit connecting to both ends of a transmission line is fluctuated. SOLUTION: The transmission system 1 is provided with a transmission line 10, LSIs 30a, 30b connecting respectivelyt o both ends of the transmission line 10, and a reference level generating voltage divider 130 that is connected to the LSIs 30a, 30b. The reference level generating voltage divider 130 generates a reference level based on both power supply voltages of the LSIs 30a, 30b. The LSI 30a has a reference voltage adjustment circuit 110a that adjusts a reference voltage of a reference output 38a of an input circuit 80a based on the reference voltage (that is similar to the case with the LSI 30b). Thus, even when a power supply voltage between the LSIs is fluctuated, a maximum input difference voltage is ensured. Thus, malfunction hardly takes place even when the amplitude of the transmission signal is decreased and low power consumption and high rate signal transmission are attained.

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