专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2002133878A NON-VOLATILE SEMICONDUCTOR MEMORY CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JP2002133878A
公开(公告)日：2002-05-10
申请号：JP2000322782
申请日：2000-10-23
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： TANIGAWA HIROYUKI , TANAKA TOSHIHIRO , SHINAGAWA YUTAKA , KAWAJIRI YOSHIKI , FUJITO MASAMICHI
IPC分类号： G11C16/02 , G06F15/78 , G11C16/06 , G11C16/14 , G11C16/30 , G11C16/34
摘要： PROBLEM TO BE SOLVED: To solve such a problem that in a conventional microcomputer incorporating a flash memory and employing a system in which a CPU controls a write-in pulse, since the CPU estimates the worst case about a characteristic of an element and power source voltage and decides a finish time, much wasteful waiting time is caused and an over-head time accompanying communication between the CPU and the memory is included in a required time. SOLUTION: The non-volatile semiconductor memory circuit is provided with a control register (CRG) for indicating basic operation such as write-in, read-out, or the like, a boosted voltage reaching detecting circuit (32) detecting whether voltage of a boosting circuit (31) reaches the prescribed level or not, circuits (21, 34) counting an applied time of write-in voltage and erasure voltage, circuits (22, 35) detecting the finish of write-in and erasure, each operation is progressed automatically by only setting operation indication to the control register, and finish is informed by setting a finish flag (FLAG) provided in the control register after finish of operation.

2. 发明专利

JPH10162587A FERROELECTRIC MEMORY 失效
公开(公告)号：JPH10162587A
公开(公告)日：1998-06-19
申请号：JP31460996
申请日：1996-11-26
申请人： HITACHI LTD
发明人： TANIGAWA HIROYUKI , TAKEUCHI MIKI , SHIMAZAKI YASUHISA , YAMADA KOSHI , NISHIMOTO JUNICHI
IPC分类号： G11C14/00 , G11C11/22 , H01L21/8242 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To reduce the access time of a plate drive type ferroelectric memory. SOLUTION: A memory cell consists of one MOS transistor QM and one ferroelectric capacitor CFE, and a plate line PL is arranged in parallel with a word line WL. After a bit line BL is precharged to a power supply potential, the word line WL is activated and a memory cell MC is read, and then the plate line PL is driven before writing data. The other edge of the plate line PL is maintained at a ground voltage by a plate potential stabilization circuit PS from the drive of the word line to that of the plate line, thus preventing the potential fluctuation of the plate line PL due to the drive of the word line and increase in an access time due to the potential fluctuation.

3. 发明专利

JPH10112191A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH10112191A
公开(公告)日：1998-04-28
申请号：JP26406596
申请日：1996-10-04
申请人： HITACHI LTD
发明人： TAKEUCHI MIKI , NISHIMOTO JUNICHI , SHIMAZAKI YASUHISA , YAMADA KOSHI , TANIGAWA HIROYUKI
IPC分类号： G11C14/00 , G11C11/22 , H01L21/8246 , H01L27/10 , H01L27/105
摘要： PROBLEM TO BE SOLVED: To maintain the high speed property of flip-flop circuits at the time of a normal operation by separating ferroelectric capacitors for retaining nonvolatility with a switching circuit. SOLUTION: A cache memory array S-MA is constituted of a word line WSO or the like, a bit line pair BLi/BLi or the like and a cache memory cell matrix arranged at intersections of word lines and bit line parts. An amplifier part SA-B detects and amplifies information of cache memory cells to output them to output lines Doi. A ferroelectric substance memory array F-MA is constituted of a work line WFO or the like, a bit line pair BLi/BLi or the like and a ferroelectric substance cell matrix arranged at intersections of word lines and bit line pairs and is arranged at a side opposite to the amplifier part SA-B with respect to the cache memory array S-MA via a switching circuit SWF. When the switching circuit SWF is turned on, the high speed property as a cache memory is not hindered by electrically separating the ferroelectric substance memory array F-MA from the cache memory array S-MA.

4. 发明专利

JPH11296196A SOUND ENCODING METHOD AND SOUND ENCODER 失效
公开(公告)号：JPH11296196A
公开(公告)日：1999-10-29
申请号：JP10096198
申请日：1998-04-13
申请人： HITACHI LTD
发明人： SHIMAZAKI YASUHISA , HATANO YUJI , NISHIMOTO JUNICHI , YAMADA KOSHI , TAKEUCHI MIKI , TANIGAWA HIROYUKI , SEKINE HIDETOSHI
IPC分类号： G10L19/04 , H03M7/30 , G10L9/14
摘要： PROBLEM TO BE SOLVED: To reduce power consumption at the time of sound encoding processing by reducing the operation quantity of sound encoding processing, when the sound is encoded by using a code note consisting of the correspondence tables of sound source parameters and codes. SOLUTION: When sound encoding is started, a sound parameter 101d is read out from a code note 101, the sound is reproduced by using a synthesis filter 300, an error from the inputted sound is evaluated by an error evaluation device 301, the evaluated value is compared with a threshold value ε, when the former is smaller than the latter, and a code 101c corresponding to sound source parameters at the time is outputted to the outside. When the evaluated value is larger than the threshold value ε, it is stored in a register 102b, and updated to the minimum successively or all are stored.

5. 发明专利

JPH11232884A NONVOLATILE MEMORY DEVICE 失效
公开(公告)号：JPH11232884A
公开(公告)日：1999-08-27
申请号：JP2747198
申请日：1998-02-09
申请人： HITACHI LTD
发明人： TAKEUCHI MIKI , TANIGAWA HIROYUKI
IPC分类号： G06F12/14 , G06F21/24 , G11C16/02
摘要： PROBLEM TO BE SOLVED: To provide a device having an access limit and which releases the limit only for a prescribed user by utilizing a password stored in a part of plural memory cells for releasing the access limit in a first access permission means and utilizing none of information stored in plural memory cells in a second access permission means. SOLUTION: A password access permission circuit 52 uses the passwords DoP(1)-DoP(s) stored in a password storage area 11 of a nonvolatile memory array 10 and internal write-in signals Di(1)-Di(s) answering to the data DQ(1)-DQ (s) imparted from the outside generated in an input buffer 24 to make signal P2 high level and generates the information DiP(1)-DiP(s) to be rewritten, An X address buffer 30 latches address signals A(1)-A(n) from the outside by a timing signal XL to generate X address signals AX(1)-AX(s).

6. 发明专利

JP2001157437A CHARGE-PUMPING BOOSTING CIRCUIT 失效
公开(公告)号：JP2001157437A
公开(公告)日：2001-06-08
申请号：JP33381799
申请日：1999-11-25
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： TANIGAWA HIROYUKI , FUJITO MASAMICHI
IPC分类号： H02M3/07
摘要： PROBLEM TO BE SOLVED: To provide a charge-pumping boosting circuit in which a reduction in the area of a power-supply circuit is realized by relaxing the degradation of a boosting efficiency due to the threshold value of a switching MOS transistor. SOLUTION: The charge-pumping boosting circuit is provided with charge pumping capacitors C1 to Cn. The boosting circuit is provided with switching MOS transistors MN0 to MNn. The boosting circuit is provided with gate boosting means GC1 to GCn which boost gates of the switching MOS transistors. The charge pumping capacitors are driven by a clock CLK1 and a clock CLK2 at a voltage amplitude generated by supplying a first voltage to a clock generating circuit A. The gate boosting means are driven by the clocks CLK1, CLK2, at a voltage amplitude generated by supplying a second voltage to a clock generating circuit C. As a result, a voltage VOUT is generated.

7. 发明专利

JP2000100176A FERROELECTRIC MEMORY 失效
公开(公告)号：JP2000100176A
公开(公告)日：2000-04-07
申请号：JP27241698
申请日：1998-09-28
申请人： HITACHI LTD
发明人： TAKEUCHI MIKI , TANIGAWA HIROYUKI
IPC分类号： G11C14/00 , G11C11/22 , H01L27/10
摘要： PROBLEM TO BE SOLVED: To promote the decrease in voltage and power consumption by improving the reliability in a ferroelectric memory that is in a plate line drive system and has a dummy cell for preventing the compression of the amount of signal of a bit line, and a single-chip microcomputer or the like for mounting it. SOLUTION: A ferroelectric memory is provided with a memory cell array ARYR where a ferroelectric memory cell MC is arranged in a lattice as its basic component and is provided with a dummy cell DC for preventing the compression of the amount of signal of complementary bit lines DL1*-DLn* due to the coupling of ferroelectric capacitors Ct and Cb. In the ferroelectric memory, the other electrodes of ferroelectric capacitors Ct' and Cb' for composing the dummy cell DC are commonly coupled, and a dummy plate line DPL that is set to a low-level selection level essentially at the same timing as the specified bit of plate lines PL1-PLm for composing the memory cell array ARYR is returned to the high-level non-selection level immediately before a sense amplifier drive signal SASB is set to a low level and a unit sense amplifier UA of a sense amplifier SAR is set to an operation state.

8. 发明专利

JPH10112190A NONVOLATILE FERROELECTRIC SUBSTANCE MEMORY 失效
公开(公告)号：JPH10112190A
公开(公告)日：1998-04-28
申请号：JP26406496
申请日：1996-10-04
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TAKEUCHI MIKI , YOSHIDA HIROSHI , TANIGAWA HIROYUKI
IPC分类号： G11C14/00 , G11C11/22
摘要： PROBLEM TO BE SOLVED: To obtain a ferroelectric substance memory suitable for a low voltage operation by setting an accumulation potential to two values of a voltage higher than a power source potential and 0V at the time of rewriting information. SOLUTION: In an information rewriting operation, a word line W1 is activated in a state in which bit line pair BL1, BB1 are precharged to the half of a power source voltage Vcc. Potentials of 0V or Vcc are complementary held in accumulation parts SN(1, 1) SB(1, 1) and a signal voltage is generated in between the bit line pair BL1, BB1 by the activation of the work line W1. A sense amplifier SA1 amplifies this signal to hold it at the potential of 0V or Vcc. When a rewriting voltage is applied on the bit line pairs BL1, BB1, the rewriting of information is executed. Here, a voltage Vbh higher than a voltage in which the power source voltage Vcc and threshold voltages of switching transistors are added is applied as the rewriting voltage. Then, either the SN(1, 1) or the SB(1, 1) of the accumulation parts becomes an accululation potential near to the voltage Vbh.

9. 发明专利

JPH1097472A SYSTEM INCLUDING FERROELECTRIC MEMORY 失效
公开(公告)号：JPH1097472A
公开(公告)日：1998-04-14
申请号：JP25126296
申请日：1996-09-24
申请人： HITACHI LTD
发明人： TAKEUCHI MIKI , TANIGAWA HIROYUKI
IPC分类号： G06F12/16 , G06F11/10 , G11C11/22 , G11C11/401 , G11C14/00 , G11C29/42
摘要： PROBLEM TO BE SOLVED: To provide the system, including the ferroelectric memory, which greatly reduce the probability that large damage to the system is caused by a soft error of the ferroelectric memory and neither decreases the operating speed nor increases the chip price. SOLUTION: In the ferroelectric memory 120, a rewriting inhibited area 122 where an OS(operating system) and application are stored and a rewriting permitted area 122 as a work area are set. The rewrite inhibited area 122 includes a parity bit area 125 and an error correcting process which uses it is performed almost once a day by a CPU 110. A correction processing start command is associated with a switch (including a power switch). In this constitution, even if the ferroelectric memory 120 malfunctions, the function of the system can be restored and there is not problems such as a decrease in operating speed and an increase in chip area unlike a case wherein an ECC circuit(error correcting circuit) is provided.

10. 发明专利

JP2002324858A NONVOLATILE SEMICONDUCTOR MEMORY, ITS DATA DELETION METHOD, INFORMATION MANAGEMENT PROCESSING DEVICE AND NONVOLATILE STORAGE DEVICE SYSTEM 失效
公开(公告)号：JP2002324858A
公开(公告)日：2002-11-08
申请号：JP2001127205
申请日：2001-04-25
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： UMEMOTO YUKIKO , TANAKA TOSHIHIRO , TANIGAWA HIROYUKI , SHINAGAWA YUTAKA
IPC分类号： G11C16/04 , G06F15/78 , G11C8/12 , G11C16/02 , G11C16/16 , H01L21/8238 , H01L21/8247 , H01L27/092 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To shorten the deletion time of the data of a nonvolatile storage device such as a flash memory (EEPROM). SOLUTION: When the data written in a memory cell MC0 out of flash memory cells MC0-2 formed through a separation area NiSO on a semiconductor substrate PSUB are deleted, a p type well PWL0 forming the memory cell MC0 is boosted to 10 V, in addition, the separation area NiSO is boosted up to 12 V by utilizing a voltage application means different from a means for applying voltage on the p type well PWL0. As the result, since parasite capacities Ca1 , Ca2 produced between each of the p type well PWL1, 2 and the separation area NiSO and a parasite capacity Cb produced between the separation area NiSO and the semiconductor substrate PSUB are charged by the voltage application means, a time necessary for charge of the parasite capacities can be reduced and the deletion time can be shortened.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式