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1. 发明专利

JPH11307625A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH11307625A
公开(公告)日：1999-11-05
申请号：JP11460998
申请日：1998-04-24
申请人： HITACHI LTD
发明人： MINE TOSHIYUKI , YOKOYAMA NATSUKI , SUDO ITSUKI , FUJISAKI KOJI
IPC分类号： H01L21/76 , H01L21/316
摘要： PROBLEM TO BE SOLVED: To avoid the appearance of voids or seams and increase in yield at the processing of a gate electrode by using an Si and Si3 N4 films as the base for depositing an O3 -TEOS (tetraethoxysilane) on, and filling Si recesses having the opening width of a specified value or below and the depth of a specified value or below with O3 -TEOS. SOLUTION: An Si substrate 101 is thermal oxidized to form an SiO2 film 102. After that, an Si3 N4 film 103 is deposited, and processed into a specified pattern. Then, with the patterned Si3 N4 film 103 as a mask, the Si substrate 101 is dry etched to form Si recesses 105 having an opening width of 200 nm or below and the depth of 400 nm or below. Next, an SiO2 film 106 is formed in the Si recesses 105, then the SiO2 film 106 is removed to exposed the Si recessed 105, and then the Si recesses are filled with an O3 -TEOS film 107 by CVD using TEOS and O3 . By this method, an yield at the time of processing a gate electrode can be increased without generating voids or seams.

2. 发明专利

JPH11233516A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH11233516A
公开(公告)日：1999-08-27
申请号：JP2680598
申请日：1998-02-09
申请人： HITACHI LTD
发明人： KUSUKAWA KIKUO , SUDO ITSUKI , NISHIDA AKIO , KIMURA SHINICHIRO , HONMA YOSHIO
IPC分类号： H01L21/302 , H01L21/304 , H01L21/3065 , H01L21/3205 , H01L21/3213
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing semiconductor devices, with which excellent surface planarization by polishing can be achieved without being influenced by the pattern widths. SOLUTION: On a semiconductor substrate 1 having protruding parts and indenting parts, a first and a second stopper layers 3 and 7, made of a material that is hard to be polished, are formed on the protruding parts and on an insulating films 6 buried in the indenting parts, respectively, and polishing for planarization is performed after the part of the insulating film 6 that is on the protruding parts is etched off selectively. By this method, highly planarized buried films can be obtained easily, and throughput of the polishing process can be improved.

3. 发明专利

JPH03220724A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH03220724A
公开(公告)日：1991-09-27
申请号：JP1493490
申请日：1990-01-26
申请人： HITACHI LTD
发明人： YOSHIGAMI JIRO , HIRAIWA ATSUSHI , SUDO ITSUKI
IPC分类号： H01L21/76 , H01L21/31 , H01L21/316 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/08 , H01L27/10 , H01L27/108 , H01L29/78
摘要： PURPOSE:To further miniaturize an element separation region by reducing the thickness of a gate's oxide film to 10nm and below. CONSTITUTION:An Si nitride film 103 is formed on a p-type Si substrate 101 by way of a thin Si oxide film 102. A second nitride film 104 after it is processed and an Si oxide film 105 are continuously deposited thereon and the oxide film 105 is dry-etched so that wet etching may be carried out with the Si nitride film, using the dry-etched film 105 as a mask. The Si nitride film 104 and the Si oxide film 105 are adapted to remain on the side wall of the Si nitride film 103. Then, after the oxide film 105 is removed, a thick oxide film 106 (field oxide film) is selectively formed. After the Si nitride films 103 and 104 are removed, the Si oxide film 102 is removed and a contamination layer on the surface of the Si substrate an then a gate oxide film 108, which is 10nm thick and below, is formed based on a thermal oxidation process. Furthermore, polycrystalline Si 109 is formed thereon. After the crystal is made to be conductive based on a diffusion process and then processed, an MOS capacitor is completed, which makes it possible to miniaturize the element separation region.

4. 发明专利

JPH01243447A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01243447A
公开(公告)日：1989-09-28
申请号：JP6938188
申请日：1988-03-25
申请人： HITACHI LTD
发明人： SUDO ITSUKI , KAWAMOTO YOSHIFUMI
IPC分类号： H01L21/76
摘要： PURPOSE:To prevent intrusion of bird's beaks into an element region and to improve the degree of integration of a device by composing a first oxidation- resistant insulating film of a compound of Si, O and N as major elements. CONSTITUTION:The film of the intermediate compound (silicon oxynitride) of an SiO2 film and an Si3N4 film is used as a first oxidation-resistant insulating film. Consequently, when the oxynitride film is employed, intrusion into an element region of bird's beaks at the time of selective oxidation can be prevented by thickening the film thickness of oxynitride, and membrane stress is made smaller than an Si3N4 film formed through a CVD method, thus obviating the occurrence of a crystal defect in an Si substrate on selective oxidation, then reducing the leakage currents of a semiconductor element. Accordingly, the degree of integration of a semiconductor device is improved, and the leakage currents of the semiconductor element are lowered.

5. 发明专利

JPH1041507A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH1041507A
公开(公告)日：1998-02-13
申请号：JP19729396
申请日：1996-07-26
申请人： HITACHI LTD
发明人： ADACHI TETSUO , KATO MASATAKA , SUDO ITSUKI
IPC分类号： H01L21/316 , H01L21/336 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To ensure the withstand voltage of a diffusion layer, and to prevent the fluctuation of MOS transistor characteristics and the lowering of element isolation resistivity by forming a structure in which a gate electrode and an element isolation region, and a diffusion layer and the element isolation region do not come into contact with each other. SOLUTION: A gate oxide film 2, a polysilicon film 3 and Si3 N4 insulating film 14 are coated on a P-type semiconductor substrate 1 by conducting a sacrificial oxide film formation and removing process, the polysilicon film and the Si3 N4 insulating film are processed on the part which becomes an active region by photoetching, and an Si3 N4 film 15 is formed on the whole surface. Anisotropic dry etching is conducted in such a manner that the Si3 N4 insulating film 15 is left on the side face only of the polysilicon film 3 and the Si3 N4 film 14, a channel stopper layer 4 and an element isolation layer 5 are formed, and the Si3 N4 film on the polysilicon 3 and the Si3 N4 film 15 on the side wall are removed. Accordingly, by providing a side wall consisting of a CVD insulating film, the threshold value of the MOS transistor in a microscopic region can be stabilized, and the lowering of the withstand voltage of the diffusion layer on an element isolation end part can be prevented.

6. 发明专利

JPH0883589A SCANNING ELECTRON MICROSCOPE 失效
公开(公告)号：JPH0883589A
公开(公告)日：1996-03-26
申请号：JP21845494
申请日：1994-09-13
申请人： HITACHI LTD
发明人： NINOMIYA TAKESHI , SUDO ITSUKI , KURE TOKUO
IPC分类号： G01N23/225 , H01J37/256
摘要： PURPOSE: To provide an observing device for a semiconductor wafer in a semiconductor manufacturing process. CONSTITUTION: An electron beam 13 is radiated to a sample 5, and X-rays 14 and an electron 15 emitted from a surface of a sample 4 by electron beam radiation are detected by using an X-ray detector 7 and a detector 6. Energy of an electron beam 13 can be optionally set in a range not higher than 300keV. Therefore, since the energy of the electron beam is set according to an observing object or a target and a secondary electron, a tertiary electron, a reflected electron and X-rays from the bottom surface of a micropore can be detected, an inside shape of the micropore and a residual film can be observed in detail by the same device.

7. 发明专利

JPH0883588A X-RAY ANALYZER 失效
公开(公告)号：JPH0883588A
公开(公告)日：1996-03-26
申请号：JP21845394
申请日：1994-09-13
申请人： HITACHI LTD
发明人： SUDO ITSUKI , KURE TOKUO , NINOMIYA TAKESHI
IPC分类号： G01N23/225 , H01J37/244 , H01J37/252
摘要： PURPOSE: To eliminate adverse influence of a radiating electron beam of an X-ray detector on an orbit by constituting a part facing at least the electron beam central axis of an X-ray detecting means out of a nonmagnetic material. CONSTITUTION: An accelerated electron beam 1 is perpendicularly irradiated to a surface of a sample 2, and a beam diameter of the electron beam 1 is made smaller than the size of an accumulating area of a residual film. Accelerating energy of an accelerating line 1 is controlled in 5kev or less, and the focusing and accleration are performed by an objective lens 3 and a condenser lens 4. When the electron beam is irradiated, X-rays 5 are generated from the residual film, and the X-rays 5 are detected by an X-ray detector 6 near the axis of the electron beam 1 in an intermediate position between the objective lens 3 and the condenser lens 4. The detector 6 has an energy analyzing function, and the arranging position is brought close to the electron beam 1 as much as possible, and the X-rays 5 are made incident on a light receiving surface. Therefor, the detector 6 is housed in a housing 9 composed of a nonmagnetic material, and is arranged very close to the electron beam central axis between the lenses 3 and 4.

8. 发明专利

JPH06151578A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH06151578A
公开(公告)日：1994-05-31
申请号：JP29504292
申请日：1992-11-04
申请人： HITACHI LTD
发明人： SUDO ITSUKI , IIJIMA SHINPEI , KURE TOKUO , KAWAMOTO YOSHIFUMI
IPC分类号： H01L21/76 , H01L21/316
摘要： PURPOSE:To raise the interelement isolation performance of interelement isolating regions having different areas by forming a first insulating film on the main surface of a semiconductor substrate, and forming a second insulating film for element isolation in the groove made in the substrate. CONSTITUTION:Since the interval is narrow in a minute selement isolating region, an Si3N4 film 104 and an SiO2 film 105 are not exposed from the surface of an Si substrate, being buried between a first SiO2 film 102 and a first Si3N4 film 103. A groove 107 is made only in a minute element isolating region by performing reactive ion etching with the Si3N4 film 104 as a mask. An SiO2 film 108 is made on the inner face of the groove by oxidizing the surface of the groove 107, and then a first SiO2 film 106 for element isolation and, at the bottom of an Si groove 107, a boron-implanted layer for channel stopper are made by implanting boron ions. A second SiO2 film 109 is made all over the surface by the CVD method using B and BPSG. The second SiO2 film 109 for element isolation is left only in the groove 107 by etching it until the surface of the substrate 101 is exposed.

9. 发明专利

JPH02240944A METHOD FOR IMPROVING QUALITY OF GROOVE-FILLING INSULATING FILM AND INTERELEMENT ISOLATING METHOD 失效
公开(公告)号：JPH02240944A
公开(公告)日：1990-09-25
申请号：JP6097089
申请日：1989-03-15
申请人： HITACHI LTD
发明人： IIJIMA SHINPEI , SUDO ITSUKI , KAWAMOTO YOSHIFUMI , SUZUKI TADASHI , KASHU NOBUYOSHI
IPC分类号： H01L21/76 , H01L21/316
摘要： PURPOSE:To eliminate an interface (defect) at the central part of a groove which is formed in a stage wherein a insulating film is deposited in the groove and to prevent the formation of a gouged part by filling the insulating film in the groove, and thereafter introducing germanium into the insulating film. CONSTITUTION:A groove 2 is formed. An insulating film 3 is formed. Thereafter germnium ions are implanted 5 at the desired position of the insulating film 3 in the groove. Thus the formation of this device is achieved. The implanting conditions are as follows: ion accelerating energy is made to be 0.4MeV or more and 2.5MeV or less; and an ion dosing quantity is made to be in a region of 1X10 -5X10 cm . Even if a heterogeneous region is present in the insulating filled in the groove, a homogeneous part can be formed. A gouged part is not formed in wet etching at the later step. The formation of the insulating film 3 which is embedded in the groove 2 and whose surface is very flat can be realized.

10. 发明专利

JPS62159434A METHOD FOR WORKING THIN FILM 失效
公开(公告)号：JPS62159434A
公开(公告)日：1987-07-15
申请号：JP55786
申请日：1986-01-08
申请人： HITACHI LTD
发明人： HONMA YOSHIO , NISHIDA TAKASHI , TSUNEKAWA SUKEYOSHI , YOKOYAMA NATSUKI , MORIZAKI HIROSHI , SUDO ITSUKI
IPC分类号： H01L21/302 , H01L21/3065
摘要： PURPOSE:To prevent a substrate from damaging by etching a polymer resin layer for flattening a coated film layer under the condition that the etching velocities of a projecting pattern and a second polymer resin layer become equal. CONSTITUTION:Projecting patterns 31a-31d made of polyimide are formed on an Si substrate 30 covered by an SiO2 film having approx. 20nm of thickness on the surface, and covered with a coating layer 32 made of SiO2 thereon. A first polymer resin layer 36 is formed on the layer 32. Then, a second polymer resin layer 35 made of polyimide resin having excellent flatness is formed. It is etched back by reactive sputter etching using gas mixed with approx. 3% of O2 in C2F6. The etching velocity at this time is approx. 250nm/min for the SiO2 and approx. 200nm/min for both the first and second layers 35, 36. When the layer 32 becomes 0.8mum of thickness, it is etched back. Then, the patterns are removed, and predetermined holes and groove patterns are formed in the layer 32 without damaging the substrate 30.

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