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1. 发明专利

JP2004140117A Multilayer circuit board, and method of manufacturing the same 审中-公开
公开(公告)号：JP2004140117A
公开(公告)日：2004-05-13
申请号：JP2002302229
申请日：2002-10-16
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： ISHIZAKI KOKI , SHIRATO TAKESHI
IPC分类号： H01C17/242 , H05K1/09 , H05K1/16 , H05K3/28 , H05K3/46
CPC分类号： H01C17/242 , H05K1/092 , H05K1/167 , H05K3/4644 , H05K2201/093 , H05K2201/09663 , H05K2201/0969 , H05K2203/107 , H05K2203/171
摘要： PROBLEM TO BE SOLVED: To provide a thin, lightweight and low price multilayer circuit board of a simplified structure by simplifying the trimming process without occurrence of a short circuit which is generated by a conductive substance of the fused resistance body having reached a conductor of the lower layer when the electrical characteristic of the circuit is adjusted by trimming the resistance body. SOLUTION: The multilayer circuit board 1 is formed of a first conductor layer 3 arranged on an insulated substrate 2, an insulator 5 allocated on the first conductor layer 3, a resistance body 9 allocated on the insulator 5, and second conductor layers 7, 8 which hold the resistance body 9 and are connected thereto. This multilayer circuit board 1 is capable of adjusting the electrical characteristic of the circuit by trimming the resistance body 9. In this multilayer circuit board 1, the portion of the first conductor layer 3 corresponding to the first trimming portion 10 of the resistance body 9 is formed of a first insulation region 6. COPYRIGHT: (C)2004,JPO

2. 发明专利

JPS5381094A PRODDUCTION OF SILICONNCONTAINED ALUMINUM WIRINGS 失效
公开(公告)号：JPS5381094A
公开(公告)日：1978-07-18
申请号：JP15653076
申请日：1976-12-27
申请人： HITACHI LTD
发明人： TOMOSAWA AKIHIRO , NARUSHIMA MASACHIKA , SHIRATO TAKESHI
IPC分类号： H01L21/3205 , H01B1/00 , H01B1/02 , H01L21/28 , H01L23/52
摘要： PURPOSE:To obtain satisfactory ohmic contacts and obtain Al wiring structure having a uniform Si distribution by forming an Al film without containing Si on a first Al film containing Si, selectively removing the first and second Al films to make wiring patterns thereafter subjecting the films to annealing treatment.

3. 发明专利

JPH0216593B2 失效
公开(公告)号：JPH0216593B2
公开(公告)日：1990-04-17
申请号：JP11171282
申请日：1982-06-30
申请人： HITACHI LTD
发明人： SATO RYOHEI , SHIRATO TAKESHI , SUGISHITA NOBUYUKI , TSUNODA TOYOJI
IPC分类号： H05K3/46 , H05K1/09 , H05K3/12

4. 发明专利

JPS61187342A CHIP RECOGNITION USING TRANSPARENT CHIP TRAY 失效
公开(公告)号：JPS61187342A
公开(公告)日：1986-08-21
申请号：JP2627885
申请日：1985-02-15
申请人： HITACHI LTD
发明人： OKUDA KENICHI , SHIRATO TAKESHI , NEMOTO SHIGERU , WATANABE AKITOMO
IPC分类号： H01L21/673 , H01L21/00 , H01L21/67 , H01L21/68
摘要： PURPOSE:To contrive to shorten the time to mount semiconductor chips on a transparent tray in the normal direction by a method wherein the chips are housed in the pockets of the tray and the images of the chips are directly taken in from the lower direction of the tray. CONSTITUTION:When the images of semiconductor chips 11 are taken in, the pockets 12, wherein the semiconductor chips 11 are housed, of a transparent chip tray 10 are fed one by one by controlling the X-Y stand. At this time, the center of the point of an attracting head 5 is made to coincide with the center of each pocket 12, the chips only having images turning to a direction different from the normal direction among the images of the chips 11, which are taken in from the lower direction of the tray 10, are mounted on the tray 10 in the normal direction by making the head 5 revolve to the direction of theta deg., and at the same time, the correction of the positions of the chips 11 is performed. The images of the chips are directly taken in by an image pickup camera 20 from the lower direction of the tray 10. The tray 10 is made of transparent resin having a volume resistivity of 1X10 -1X10 , the pockets 12 are arrayed on the tray 10 in a lattice type, the wall thickness of the tray is uniformly formed to eliminate the tray's own lens action, and moreover, the tray is formed in a double bottom to prevent the bottom surface thereof from being damaged. According to this way, the chips can be recognized in a state intact being housed in the pockets of the tray and the time to mount the chips on the tray in the normal direction can be shortened.

5. 发明专利

JPS57210656A MANUFACTURE OF HYBRID INTEGRATED CIRCUIT 失效
公开(公告)号：JPS57210656A
公开(公告)日：1982-12-24
申请号：JP9385781
申请日：1981-06-19
申请人： HITACHI LTD
发明人： SHIRATO TAKESHI , NIIZAKI SHINYA , HIROTA KAZUO , ISHI ICHIROU
IPC分类号： H01C17/06 , H01L21/70 , H01L27/01
摘要： PURPOSE:To improve the reliability of a hybrid integrated circuit by forming a plurality of circuit elements of the integrated circuit in an integrated state and then cutting it into a plurality, thereby reducing the irregularity of the circuit elements. CONSTITUTION:An electrode 12 is formed in a predetermined pattern on an insulative substrate 10, a resistor 13 is printed and baked to cross the electrode, is divided into a plurality of resistors via trimming grooves 15, and an overcoating glass 15 is then printed and baked, thereby forming a thick film resistor of a hybrid integrated circuit. In this manner, the irregularity in the characteristics of the elements is eliminated, thereby enhancing the reliability.

6. 发明专利

JPS5570057A PREPARATION OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS5570057A
公开(公告)日：1980-05-27
申请号：JP14342478
申请日：1978-11-22
申请人： HITACHI LTD
发明人： TOMOSAWA AKIHIRO , SHIRATO TAKESHI , SAKAI YOSHIO
IPC分类号： H01L27/04 , H01L21/822 , H01L27/06 , H01L29/78
摘要： PURPOSE:To improve the accuracy of patterning, by selectively doping impurities to polysilicon after patterning the polysilicon when using the polysilicon as an electrode, wiring or resistance as MOSIC. CONSTITUTION:A thick field SiO2 film 12 and a thin gate SiO2 film 12A are formed on a surface of a P-type Si substrate 10, and the whole surface is coated with a poly Si layer 14. The poly Si layer hardly contains impurities. Other portions except a poly Si layer 14A for a gate electrode and a poly Si layer 14B for resistance are removed by patterning the poly Si layer 14 by means of a photo-resist mask. The poly Si layer 14B for high resistance is coated with an Si3N4 film 16 and an SiO2 film 18, and the gate electrode 14A is doped and a source 20 and a drain 22 are doped, thus completing a MOSIC. Consequently, the high accuracy of finishing can be obtained because poly Si is patterned under a condition that impurities are hardly contained.

7. 发明专利

JPS54152967A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS54152967A
公开(公告)日：1979-12-01
申请号：JP6109578
申请日：1978-05-24
申请人： HITACHI LTD
发明人： SHIRATO TAKESHI , TOMOSAWA AKIHIRO , KIYONO MASAMI
IPC分类号： H01L21/52 , H01L21/58
摘要： PURPOSE:To prevent n-type inversion and to improve assembly efficiency by previously providing a Cr-Ni-Pd thin film to the reverse surface of a p-type Si substrate and by connecting Au to an Au layer on a support member via Au or an Au-Sn foil. CONSTITUTION:Adhesion between the p-type Si substrate and Ni is reinforced by Cr, Ni prevents Au immersing into Si, and Pd improves the wetting properties of Ni to Au or Au-Sn. consequently, Au diffuses into p-type Si not to form any n-type inversion layer, and pellet bonding can be done in a contituous furnace, so that assembly efficiency will improve greatly.

8. 发明专利

JP2003059968A High-frequency semiconductor module and packaging method therefor 审中-公开
标题翻译：高频半导体模块及其封装方法
公开(公告)号：JP2003059968A
公开(公告)日：2003-02-28
申请号：JP2001241074
申请日：2001-08-08
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： EGUCHI KUNIYUKI , NAKAZAWA TERUMI , SHIRATO TAKESHI
IPC分类号： H01L23/12 , H01L21/60
CPC分类号： H01L2224/05554 , H01L2224/45 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/48472 , H01L2224/49175 , H01L2224/73265 , H01L2924/14 , H01L2924/1423 , H01L2924/3011 , H01L2924/00014 , H01L2924/00 , H01L2924/20753
摘要： PROBLEM TO BE SOLVED: To provide a packaging method for electrically, simply, and accurately connecting a conductor on substrate wiring having a high-frequency line to a semiconductor bare ship and/or a chip component such as capacitor, reducing the transmission loss of a signal at a connection section furthermore, and at the same time securing connection reliability in a semiconductor module for high frequencies used for an automobile radar, a radio LAN, and the like.
SOLUTION: A conductor on substrate wiring having a high-frequency line is electrically connected to a semiconductor bare chip and/or a chip component such as a capacitor by a TAB tape with a one-side conductor layer.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：为了提供一种用于电气地，简单地且准确地将具有高频线的衬底布线上的导体连接到半导体裸船和/或诸如电容器的芯片组件的封装方法，降低了传输损耗信号，并且同时确保用于汽车雷达，无线电LAN等的高频用半导体模块中的连接可靠性。解决方案：具有高频线的衬底布线上的导体通过具有单面导体层的TAB带电连接到半导体裸芯片和/或诸如电容器的芯片组件。

9. 发明专利

JPS5936902A Thick film resistance circuit 失效
标题翻译：厚膜电阻电路
公开(公告)号：JPS5936902A
公开(公告)日：1984-02-29
申请号：JP14615582
申请日：1982-08-25
申请人： Hitachi Ltd
发明人： SHIRATO TAKESHI , NIIZAKI SHINYA , HIROTA KAZUO
IPC分类号： H01C7/00

10. 发明专利

JP2002120195A METHOD OF MACHINING LAMINATED BOARD 失效
公开(公告)号：JP2002120195A
公开(公告)日：2002-04-23
申请号：JP2000312896
申请日：2000-10-13
申请人： HITACHI LTD , HITACHI CAR ENG CO LTD
发明人： KOSHIZAKA ATSUSHI , NAKAZAWA TERUMI , YOKOYAMA MIZUHO , SHIRATO TAKESHI
IPC分类号： B26F1/00 , H05K3/00
摘要： PROBLEM TO BE SOLVED: To provide a laminated board machining method capable of improving reliability, and improving productivity. SOLUTION: A part of a metal layer 3 and a metal plating layer 4 formed on a non-metal layer 2 is removed in a larger size than a through hole to form non-through holes 6a and 6b. Next, the through hole 9 is punched through the non-metal layer 2 using a punch 8 and a die 7 in such a way that it will not get in contact with circuit parts 5a and 5b around the non-through holes 6a and 6b.

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