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1. 发明专利

JPH0625926B2 失效
公开(公告)号：JPH0625926B2
公开(公告)日：1994-04-06
申请号：JP19480585
申请日：1985-09-05
申请人： HITACHI LTD
发明人： MATSUZAKI YOSHE , ISOBE MITSUNOBU , HAMANO JUNICHI , OSAKO KAZUYOSHI
IPC分类号： G06F15/16 , G05B19/02 , G05B19/05 , G06F15/173 , H04L12/40

2. 发明专利

JPH02227702A PROGRAMMABLE CONTROLLER 失效
公开(公告)号：JPH02227702A
公开(公告)日：1990-09-10
申请号：JP4650989
申请日：1989-03-01
申请人： HITACHI LTD
发明人： FUJIWARA KATSUHIRO , ITO ATSUSHI , OSAKO KAZUYOSHI
IPC分类号： G05B19/048 , G05B19/05 , G05B23/02 , H05K7/14
摘要： PURPOSE:To improve the packaging density of each unit and to secure the sure display of each unit state by adding a mechanism to a function unit for attachment of plural display units and providing a conduction means between the function unit and the display unit. CONSTITUTION:A control input signal (c) or a control output signal (d) is transferred between a controlled system 5 and plural input/output units 2. These units 2 are connected to a main arithmetic unit 1 serving as a function unit via an input/output bus (a) as well as to the display units 3 via the serial signal transmission lines (b). Thus the states of input/output signals of the units 2 are displayed on the units 3 respectively. Then a program monitor device 4 is connected to the unit 1 via a signal transmission line (e). Thus the unit 1 can perform its working as desired and at the same time this working state is monitored. Each unit 3 is attached to each unit 2 by means of a magnet 33x bonded on the back of the unit 3. Both units 2 of the same size are packaged with overlapping each other and each unit 3 is attached to the surface of each unit 2.

3. 发明专利

JPS60235215A INPUT SYSTEM OF SEQUENCE CONTROL PROGRAM 失效
公开(公告)号：JPS60235215A
公开(公告)日：1985-11-21
申请号：JP9028884
申请日：1984-05-08
申请人： HITACHI LTD
发明人： MATSUZAKI YOSHIE , ISOBE MITSUNOBU , HATA SEIJI , OSAKO KAZUYOSHI
IPC分类号： G05B19/05
摘要： PURPOSE:To simplify a keyboard by sharing a command key and allowing it to correspond to two kinds of languages when two kinds of language, namely, a relay ladder language and a process progression language are inputted to a programmable controller. CONSTITUTION:In a key code discriminating part 22, a key code designating a language of the source program from a keyboard 21 sets a language mode flag 24 and the other key codes are sent to an input buffer 23 as they are. A command interpreting part 25 refers to the language mode flag 24 to find the type of the language and interprets the key code in the input buffer 23 in accordance with the type of the language and generates an object program and stores it in an object buffer. If a pattern symbol key code exists in the input buffer 23, it is interpreted as a key code indicating logical relations if the relay ladder language is used; but it is interpreted as a key code indicating sequential synchronous relations if the process progression language is used.

4. 发明专利

JPS596084B2 JPS596084B2 - 失效
公开(公告)号：JPS596084B2
公开(公告)日：1984-02-09
申请号：JP9360078
申请日：1978-08-02
申请人： Hitachi Ltd
发明人： OSAKO KAZUYOSHI , TANIUCHI KATSUMI , OGAWA YASUICHIRO , OORA MASAO
IPC分类号： G05B15/02 , G05B19/05 , H03K17/28 , H03K17/296
CPC分类号： H03K17/296

5. 发明专利

JPS56143050A ASYNCHRONOUS INTERFACE DEVICE 失效
公开(公告)号：JPS56143050A
公开(公告)日：1981-11-07
申请号：JP4462680
申请日：1980-04-07
申请人： HITACHI LTD
发明人： OSAKO KAZUYOSHI
IPC分类号： G06F13/38 , G06F5/06 , G06F5/08
摘要： PURPOSE:To simplify the procedure and reduce the loss time for supplying an information consisting of n words, by connecting the transmission side with reception side via the register group storing a plurality of data constituting one information. CONSTITUTION:Registers Reg 1-Reg n of the interface IF stores the data for one word's share respectively. When the power supply is given, the counter CT7 outputs the signal (g), the peripheral device PD confirms the signal (g) and outputs the data DO and the signal (f). This is repeated for n word's share and when the write-in of data is finished for Reg 1-Reg n, PD transmits the data set completion signal (d). Then, CT7 is cleared with the synchronizing signal (e) from CPU and the signal (g) disappear and IF is switched from PD to CPU. CPU outputs the selection signal C and reads in the data for one word's share from Reg n, and every time when the data read-in is finished for one word, the signal (b) is outputs. CPU makes the read-in n times in succession, and when the read-in is finished, CT7 outputs the signal (g) and IF is again switched to PD.

6. 发明专利

JPS5543614A LOGIC ARITHMETIC UNIT 失效
公开(公告)号：JPS5543614A
公开(公告)日：1980-03-27
申请号：JP11579778
申请日：1978-09-22
申请人： HITACHI LTD
发明人： OOURA MASAO , OSAKO KAZUYOSHI
IPC分类号： G06F7/00
摘要： PURPOSE:To obtain a logic arithmetic unit which can process the Boolean algebra containing the parenthesis order in a short time and simple constitution. CONSTITUTION:Receiving 1st timing signal T1, 1st temporary memory means IRG memorizes temporarily the input information at that time point and then delivers it. In case the closing parenthesis order is received, the input information at the generating time of 2nd timing signal T2 is memorized temporarily and then delivered. Receiving 4th timing signal T4, 2nd and 3rd temporary memory parts ARG and ORG memorize temporarily the input information at that time point and deliver it. In case the open parenthesis order is received, the input information at the generating time point of 3rd timing signal T3 is memorized temporarily and then delivered. In such way, an organic connection is secured between three types of logic arithmetic means plus 1st, 2nd and 3rd temporary memory means, and these means are actuated rationally via the order signal. As a result, the number of the temporary memory means can be decreased, and thus the greater part can be shared in the operation outside and inside the parenthesis.

7. 发明专利

JPS5451334A PROTECTOR FOR MEMEORY CONTENT OF DATA MEMORY DEVICE 失效
公开(公告)号：JPS5451334A
公开(公告)日：1979-04-23
申请号：JP11682177
申请日：1977-09-30
申请人： HITACHI LTD
发明人： OSAKO KAZUYOSHI , MASUMOTO TAKEO , KITA TETSUO
IPC分类号： G06F12/16 , G06F1/30 , G11C29/00
摘要： PURPOSE:To make it possible to carry on the operation by protecting any one or several addresses preset to a data memory unit even if a power voltage after disappearing recovers to operate an initial clear circuit. CONSTITUTION:At one point in time in period T while initial clear circuit 7 is generating clear signal CL, the same address as the set address set by address setting method 11 is outputted from program memory unit 1 and applied to data memory unit 5. As a result, a write inhibit signal is applied to read-write terminal R/W of the data memory unit and the information before a power failure is maintained in this address.

8. 发明专利

JPS53120064A SEQUENCE CONTROLLER 失效
公开(公告)号：JPS53120064A
公开(公告)日：1978-10-20
申请号：JP3339977
申请日：1977-03-28
申请人： HITACHI LTD
发明人： MASUMOTO TAKEO , OSAKO KAZUYOSHI
IPC分类号： G05B15/02 , G05B19/04 , G05B19/05
摘要： PURPOSE:To effectively utilize output storage memories in a sequence controller by providing thereto means for descriminating whether the output of a logical operation processing means itself or the negated signal of same should be output based on contents stored in the output storage memories and also on input conditions including a set instruction and a reset instruction.

9. 发明专利

JP2553490B2 失效
公开(公告)号：JP2553490B2
公开(公告)日：1996-11-13
申请号：JP22125184
申请日：1984-10-23
申请人： HITACHI LTD
发明人： FUJIWARA KATSUHIRO , OKAMURA KOSUKE , OSAKO KAZUYOSHI
IPC分类号： G05B23/02 , G05B19/02 , G05B19/048 , G05B19/05

10. 发明专利

JPS61100810A Abnormality detecting method of sequence controller 失效
标题翻译：序列控制器异常检测方法
公开(公告)号：JPS61100810A
公开(公告)日：1986-05-19
申请号：JP22125184
申请日：1984-10-23
申请人： Hitachi Ltd
发明人： FUJIWARA KATSUHIRO , OKAMURA KOSUKE , OSAKO KAZUYOSHI
IPC分类号： G05B23/02 , G05B19/02 , G05B19/048 , G05B19/05
CPC分类号： G05B19/058
摘要： PURPOSE:To realize a general-purpose abnormality detecting method of a sequence controller, in which detected contents can be changed easily, by implementing a program for detecting abnormality separately from the detailed conditions of sequence controlling operations. CONSTITUTION:A programmable sequence controller is equipped with an arithmetic control section 1, program counter 2, user program memory 3, and input- output controlling section 4 and an instruction code I in a program is inputted in the arithmetic control section 1 and decoded and executed. Parts of the program other than the instruction code I are inputted in the input-output controlling section 4 as operands and sequence control is successively performed by executing the one step of a sequence controlling section. In this case, four kinds of instructions of FLOW-CHK, TS-ON, TS-OFF, and TS-END are added as instruction languages. Moreover, a memory, in which the state transition of expected sequence control is written, is used and the transition read out from the memory is compared with the current transition. Therefore, the transition abnormality of the sequence controlling state can be monitored surely.
摘要翻译：目的：为了实现可以容易地改变检测内容的序列控制器的通用异常检测方法，通过实施与序列控制操作的详细条件分开检测异常的程序。构成：可编程顺序控制器配有运算控制部分1，程序计数器2，用户程序存储器3和输入输出控制部分4，程序中的指令代码I被输入运算控制部分1中，执行。通过执行序列控制部分的一个步骤，连续地执行除了指令码I之外的程序的部分作为操作数和序列控制输入到输入 - 输出控制部分4。在这种情况下，添加了FLOW-CHK，TS-ON，TS-OFF和TS-END的四种指令作为指令语言。此外，使用其中写入预期序列控制的状态转换的存储器，并将从存储器读出的转换与当前转换进行比较。因此，可以可靠地监视顺序控制状态的过渡异常。

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