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    • 1. 发明专利
    • INTER-VEHICLE DISTANCE CONTROL DEVICE
    • JPH0930288A
    • 1997-02-04
    • JP18380695
    • 1995-07-20
    • HITACHI LTD
    • ONDOU SHIGEYOSHITAKANO KAZUROHANAWA KAZUHIKONAKAMURA KAZUTOKAGUCHI KEIICHIMOJI TATSUHIKO
    • B60K31/00B60W30/00F02D29/02F02D41/14
    • PROBLEM TO BE SOLVED: To facilitate fitting and make cost lower in comparison to newly fitting the whole inter-vehicle distance control system to a vehicle previously mounted with a constant speed travel control unit by transmitting a false operation signal to the previously mounted constant speed travel control unit. SOLUTION: When an automatic constant speed travel setting switch 4a is operated and its signal is outputted to a microcomputer 1604 from an input port 1602, the same signal is transmitted to an automatic constant speed travel control device 2a from an output port 1606 so as to make constant speed travel control possible. Whether there is the danger of a collision is judged on the basis of inter-vehicle distance outputted from an inter-vehicle distance sensor input port 1608, relative speed data and vehicle speed data, and in the case of the automatic constant speed travel control device 2a being in operation, a signal for temporarily stopping constant speed travel control is transmitted to the automatic constant speed travel control device 2a from the output port 1606. In the case of no danger of a collision, a constant speed travel control restart signal is transmitted to the automatic constant speed travel control device 2a from the output port 1606.
    • 6. 发明专利
    • Semiconductor integrated circuit for communication control
    • 用于通信控制的半导体集成电路
    • JP2003271549A
    • 2003-09-26
    • JP2002075925
    • 2002-03-19
    • Hitachi Ltd株式会社日立製作所
    • KAMIMURA MINORUONDOU SHIGEYOSHI
    • G06F13/36G06F13/38H04L13/08
    • PROBLEM TO BE SOLVED: To solve the problem wherein when data bus width is expanded to attain high speed and transfer data size is enlarged, excess bytes which are originally not effective are transferred as extra data.
      SOLUTION: The bit number of transfer using a bus connecting a CPU (210) and a serial interface part (260) is expanded to an integer multiple of byte, and in transferring transmit data, the number of bytes of data is informed from the CPU to the interface part. The interface part is provided with a circuit (REG) for holding the informed data byte number, a circuit (RP) showing the byte number of transmit data read from a transmit buffer, and a comparator circuit (626) for comparing the byte numbers of the circuits. According to an output signal of the comparator circuit, a control signal is generated to a protocol control means 263.
      COPYRIGHT: (C)2003,JPO
    • 要解决的问题为了解决当数据总线宽度扩大以达到高速并且传输数据大小被扩大的问题时,原来不起作用的多余字节作为额外的数据传送。

      解决方案:使用连接CPU(210)和串行接口部分(260)的总线进行传输的位数扩展为字节的整数倍,在传送发送数据时,通知数据字节数 从CPU到接口部分。 接口部分设置有用于保持通知数据字节数的电路(REG),表示从发送缓冲器读出的发送数据的字节数的电路(RP)和比较电路(626),用于比较 电路。 根据比较器电路的输出信号,向协议控制装置263产生控制信号。版权所有(C)2003,JPO

    • 9. 发明专利
    • Semiconductor integrated circuit for communication control
    • 用于通信控制的半导体集成电路
    • JP2003303168A
    • 2003-10-24
    • JP2002107377
    • 2002-04-10
    • Hitachi Ltd株式会社日立製作所
    • ONDOU SHIGEYOSHIKAMIMURA MINORUSUZUKI TAKAYUKI
    • G06F13/38
    • PROBLEM TO BE SOLVED: To solve problems that two transmission buffers and two reception buffers, of maximum packet size, are required for conventional transmission/ reception buffer forming methods, which enlarges chip size and increases costs while enhancing transfer velocity, and that time required for data transfer can not be sufficiently abridged when transmission/reception buffers are each formed of a single buffer having storage capacity of the maximum packet size in order to reduce costs. SOLUTION: This circuit is provided with a buffer memory 610 for holding received data up until the completion of error detection/correction, a reception allowing threshold register 613 capable of setting an arbitrary threshold address in a reception buffer part 262A having a write pointer for generating write address signals and a read pointer for generating read address signals, and a comparison circuit 616 for comparing a set value of the register with the value of the read pointer. This circuit is provided with the function of allowing the reception of a next data packet when the set value of the register is equal to a read address generated by the read pointer. COPYRIGHT: (C)2004,JPO
    • 解决的问题:为了解决传统的发送/接收缓冲器形成方法需要两个传输缓冲器和两个接收缓冲器的最大包大小的问题,这扩大了芯片尺寸并增加了传输速度,同时提高了传输速度,而且 为了降低成本,发送/接收缓冲器各自由具有最大分组大小的存储容量的单个缓冲器形成时,数据传送所需的时间不能被充分地简化。 解决方案:该电路设置有缓冲存储器610,用于保持接收的数据直到完成错误检测/校正,接收允许阈值寄存器613能够在具有写入的接收缓冲器部分262A中设置任意的阈值地址 用于产生写地址信号的指针和用于产生读地址信号的读指针,以及比较电路616,用于将寄存器的设定值与读指针的值进行比较。 该电路具有当寄存器的设定值等于由读取指针产生的读取地址时允许接收下一个数据分组的功能。 版权所有(C)2004,JPO