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1. 发明专利

JPS6129974A Analog adder 失效
标题翻译：模拟添加剂
公开(公告)号：JPS6129974A
公开(公告)日：1986-02-12
申请号：JP14956484
申请日：1984-07-20
申请人： Hitachi Denshi Ltd , Hitachi Ltd
发明人： HOTTA MASAO , OKIGUCHI KOTARO , MAIO KENJI
IPC分类号： G06G7/14
摘要： PURPOSE:To make an adder act at a high speed without requiring PNP type transistor and to prevent the signal delay by connecting two or more analog input currents to the emitter of a transistor and simultaneously adding a level shift circuit. CONSTITUTION:The output of a D/A converter 2 is connected to one input terminal of an adder, while an analog input ei which should obtain a difference at the other input terminal 5 is connected to the emitter of a transistor Tr8, and the addition is executed. For a bias circuit, a constant current source 10 and diode 9 are connected to the base of the transistor Tr8 to form a base grounding-type amplifier. The added result is fetched from a collector of the Tr8 and a power source voltage is set at a high level to prevent saturating of the Tr8 in consideration of a voltage drop component to be produced at a resistance 14. Thus, since a DC off-set voltage is generated except an amplified signal voltage, a level shift circuit for consisting of a resistance 20, a capacitor 36 and a constant current source 21 is connected through a buffer amplifier 35. As a result, a high speed action can be accomplished without using a PNP type transistor and the signal delay can be prevented.
摘要翻译：目的：使加法器高速运行，无需PNP型晶体管，并通过将两个或多个模拟输入电流连接到晶体管的发射极并同时添加电平移位电路来防止信号延迟。构成：D / A转换器2的输出连接到加法器的一个输入端子，而在另一个输入端子5处应该获得差分的模拟输入ei连接到晶体管Tr8的发射极，被执行。对于偏置电路，恒流源10和二极管9连接到晶体管Tr8的基极以形成基极接地型放大器。附加结果从Tr8的集电极取出，电源电压设定为高电平，以防止在电阻14处产生的电压降分量考虑Tr8的饱和。因此，由于DC off- 除了放大的信号电压之外产生设定电压，通过缓冲放大器35连接由电阻20，电容器36和恒流源21组成的电平移动电路。结果，可以在没有使用PNP型晶体管，并且可以防止信号延迟。

2. 发明专利

JPH05130564A MOTION DETECTING CIRCUIT AND VIDEO RECORDING AND REPRODUCTING DEVICE 失效
公开(公告)号：JPH05130564A
公开(公告)日：1993-05-25
申请号：JP29327691
申请日：1991-11-08
申请人： HITACHI LTD
发明人： YOSHIZAWA KAZUHIKO , OWASHI HITOAKI , HOSOKAWA KYOICHI , YOSHIKOSHI MIYOKO , OKIGUCHI KOTARO
IPC分类号： H04N5/937 , G06T7/20 , H04N5/93 , H04N7/00
摘要： PURPOSE:To correctly detect motion even in slow motion reproduction, etc. CONSTITUTION:In the slow motion reproduction, a memory delay line 110 performs a one-field delay process for each field having a different field number, inputted at each repetitive period, from a last input field at each repetitive period of the same field and subtracters 142 and 143 detect motion signals. The motion signal of one field detected at each period is judged as a correct signal and outputted to the outside, and also stored in memory delay lines 151, 161, and 171. Then the motion signals stored in the memory delay lines 151, 161, and 171 are repeatedly outputted as correct motion signals for motion signals other than the motion signal of the one field detected at each period.

3. 发明专利

JPH02151193A DELAY QUANTITY AMPLITUDE ERROR COMPENSATION SYSTEM 失效
公开(公告)号：JPH02151193A
公开(公告)日：1990-06-11
申请号：JP30400088
申请日：1988-12-02
申请人： HITACHI LTD
发明人： OKIGUCHI KOTARO
IPC分类号： H04N5/14 , H04N9/77 , H04N9/79
摘要： PURPOSE:To eliminate a delay difference and amplitude fluctuation by adding a reference signal generated by a single reference signal generator to an information signal for each series, processing the result by a processing circuit system and using a reference signal of a processed information signal so as to detect an amplitude error of the information signal by the processing circuit system and a delay quantity error of the said information signal by the processing circuit system between the series with the reference signal of the processed information signal. CONSTITUTION:Reference signals D, E outputted from reference signal extraction circuits 22A, 22B are fed to a delay detection circuit 26. The reference signals D, E are synthesized in an OR circuit 27 by the delay quantity detection circuit 26 and the result is fed to a D flip-flop circuit 28. When a delay by a D/A converter 5B and a signal processing circuit 6B is larger than a delay by a D/A converter 5A and a signal processing circuit 6A obtained from a decode circuit 33, a switch 9 selects a delay circuit 8 equal to or closest to a difference of the delay. Thus, the delay difference in an analog information signal obtained at output terminals 10A, 10B is eliminated.

4. 发明专利

JP2510658B2 失效
公开(公告)号：JP2510658B2
公开(公告)日：1996-06-26
申请号：JP5255988
申请日：1988-03-08
申请人： HITACHI LTD
发明人： OKIGUCHI KOTARO , TAKESHITA KAZUYUKI , ETO YOSHIZUMI
IPC分类号： G11B20/10 , H04N5/91 , H04N5/92

5. 发明专利

JPH06105344A METHOD FOR GENERATING VIDEO SIGNAL 失效
公开(公告)号：JPH06105344A
公开(公告)日：1994-04-15
申请号：JP24917892
申请日：1992-09-18
申请人： HITACHI VIDEO & INF SYST , HITACHI LTD
发明人： TSUNOKA AKITOSHI , ARAI HIDEO , OWASHI HITOAKI , OKIGUCHI KOTARO
IPC分类号： H04N5/14 , H04N17/02
摘要： PURPOSE:To generate a signal by which a frequency characteristic is measured strictly with high accuracy by selecting all one period of a sine wave as an integral number of multiple of the sampling period. CONSTITUTION:A video signal is an NTSC signal and its sampling frequency is selected to be a frequency being a multiple of four of a color subcarrier frequency, that is, 14.31818MHz. Packets 1-6 of a multi-burst signal for one horizontal period are each made up of a sinusoidal wave signal, the amplitude of each packet is 50IRE and the period is a multiple of (n) ((n) is a natural number being more than 3) of a sampling period T. Sampling values S1-Sn of the sine wave at each sampling point are entirely the same for each period. Thus, the entirely same quantization error is produced at a sampling point at the same phase of each period, and amplitudes are not different from each other for each period. Furthermore, the period of a sine wave of the packets 1-6 is selected to be a multiple of (n) of the period T and the (n) is selected properly to approximate the frequency to a frequency of a conventional multi- burst signal. The waveform data are stored in a ROM of a signal generator to generate a signal by which the frequency characteristic is measured with high accuracy.

6. 发明专利

JPH05135439A SIGNAL GENERATING MEANS 失效
公开(公告)号：JPH05135439A
公开(公告)日：1993-06-01
申请号：JP29702391
申请日：1991-11-13
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST
发明人： NANAMI HIDENORI , TSUNOKA AKITOSHI , OKIGUCHI KOTARO , FUJITA KOJI , ARAI HIDEO
IPC分类号： G11B15/467 , H03L7/06 , H04N5/782 , H04N5/7826
摘要： PURPOSE:To control the period and the phase of a control signal and to stably generate the control signal by generating the control signal without being affected by the change of an external reference signal at the time of special reproducing. CONSTITUTION:When a mode signal is asynchronism, a period set value of being the same period as the period of external period information indicated by a control signal is outputted by a period set value supplying means 27. by a control signal generating means 25, since a period control signal according to the inputted period set value is outputted regardless of the external reference signal, the control signal is not affected by the disturbance of the external reference signal. When the mode signal indicates synchronism, the period set value so as to be the same period as the external reference signal is outputted by the supplying means 27. Further, when the mode signal moves from asynchronism to synchronism, by the supplying means 27, the period set value is changed and the control signal is set to the same period as the external reference signal and a phase difference is made a prescribed value. Thus, the generation control signal period and the phase are synchronized with the external reference signal without disturbing a servo control response.

7. 发明专利

JPH01227269A RECORDING AND REPRODUCING DEVICE 失效
公开(公告)号：JPH01227269A
公开(公告)日：1989-09-11
申请号：JP5255988
申请日：1988-03-08
申请人： HITACHI LTD
发明人： OKIGUCHI KOTARO , TAKESHITA KAZUYUKI , ETO YOSHIZUMI
IPC分类号： G11B20/10 , H04N5/91 , H04N5/92
摘要： PURPOSE:To prevent the degradation of picture quality due to dubbing by providing a dubbing interface circuit. CONSTITUTION:At the time of dubbing recording, a dubbing interface circuit is switched to (b) side. A regenerating digital signal is inputted from an input terminal 10, passes through the circuit 2, through a recording signal processing circuit 5 and recorded in a medium. At the time of dubbing reproducing, a dubbing interface circuit 11 is switched to (i) side, the regenerating digital signal processed by a regenerating signal processing circuit 6 passes through the circuit 11 and supplied to another recording and reproducing device from an output terminal 12. Since the regenerating digital signal does not pass through either a pre-filter 3 or an interposed filter 7 like this, the degradation of a frequency characteristic can be prevented.

8. 发明专利

JPH02195789A DELAY DIFFERENCE COMPENSATING SYSTEM 失效
公开(公告)号：JPH02195789A
公开(公告)日：1990-08-02
申请号：JP1419589
申请日：1989-01-25
申请人： HITACHI LTD
发明人： EHASHI YOSHIAKI , OKIGUCHI KOTARO
IPC分类号： H04N9/45 , H04N9/77
摘要： PURPOSE:To compensate difference in delay between analog signals with high accuracy by controlling the delay quantity of a compensation circuit corresponding to detected difference in delay by using a reference signal. CONSTITUTION:The analog signals of two systems are supplied to A/D converters 4a and 4b via input processing circuits 2a and 2b, respectively, and each signal is converted with the same phase. At such a case, delay compensation circuits 3a and 3b are provided between the circuits 2a, 2b and the converters 4a and 4b. And the reference signal is attached 1a on an input signal from a reference signal generation circuit 6a at the preceding stage of the circuit 2a, and the difference between a preset reference voltage and the voltage of the reference signal attached on the input signal is detected at a comparator 7a at a succeeding stage, and a differential voltage is detected at a delay comparator 8 as the difference in delay time, and it is supplied to the circuit 3a via an integration circuit 9, a switch change-over signal generation circuit 10, thereby, the delay quantity can be controlled.

9. 发明专利

JPS62246175A SCRAMBLING CIRCUIT 失效
公开(公告)号：JPS62246175A
公开(公告)日：1987-10-27
申请号：JP8802386
申请日：1986-04-18
申请人： HITACHI ELECTRONICS , HITACHI LTD
发明人： OKIGUCHI KOTARO , UMEMOTO MASUO , ETO YOSHIZUMI
IPC分类号： G11B20/12
摘要： PURPOSE:To easily monitor data even if blocks are transposed, by operating random numbers different by blocks in parity parts and detecting the malfunction of a time base corrector with detection omission probability 1/2n because random numbers of different blocks are applied to error detection parity and operating the same random numbers for individual block in data parts. CONSTITUTION:If a control signal phi1 is loaded for every error detection block, the signal phi1 is applied to a counter 18, and the loaded address is applied to a ROM 19 and a signal is obtained where random numbers different by blocks are operated in only parity parts by a control signal phi2 and the same random numbers for individual blocks are operated in the other parts. Consequently, even if a time base skip signal for variable speed reproducing or the like is inputted, error detection is possible because random numbers corresponding to a prescribed address are applied again in the skip position. Even if the time base is transposed in block units, data parts are correctly restored because random numbers for data parts are equal in individual blocks.

10. 发明专利

JPH0583675A SYNCHRONIZING ADDITION CIRCUIT 失效
公开(公告)号：JPH0583675A
公开(公告)日：1993-04-02
申请号：JP26688891
申请日：1991-09-19
申请人： HITACHI LTD
发明人： OKIGUCHI KOTARO
IPC分类号： H04N5/04 , H04N5/06 , H04N5/93 , H04N9/80
摘要： PURPOSE:To realize low power consumption with the minimum number of ROMs by providing a means corresponding to a circuit digitally adding a synchronizing signal to a circuit by an arbitrary DC level. CONSTITUTION:The address generated by a counter 5 is added to a common ROM 6, and latched by a latch 2. A synchronizing signal 12 adjusting the setup level by an adder 9 is added to one input of a synchronizing signal addition circuit 1, a changeover signal 13 of a video signal 11 and a synchronizing signal 12 is added, obtaining a signal 14 adding the synchronizing signal 12 to the video signal 11. Thus, the power consumption can be reduced while minimizing the ROM even when the number of systems is increased by providing the adder 9 as a means sharing the ROM 6 and making the setup level different. By digitally embedding a synchronizing signal, a circuit with stable operation can be obtained.

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