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1. 发明专利

JP2006285809A Storage device performing performance guarantee for streaming 审中-公开
标题翻译：执行性能保证的存储设备
公开(公告)号：JP2006285809A
公开(公告)日：2006-10-19
申请号：JP2005107013
申请日：2005-04-04
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NISHIMOTO SATORU , MATSUNAMI NAOTO
IPC分类号： G06F3/06 , G06F12/08
CPC分类号： G06F3/0659 , G06F3/0611 , G06F3/0689
摘要： PROBLEM TO BE SOLVED: To guarantee a transfer rate of each stream even when the plurality of streams are mixed.
SOLUTION: A disk array device required with multistream processing from a host computer performs transfer rate recognition processing for recognizing the transfer rate, drive performance and fault processing time recognition processing, size determination processing of a sequential buffer storing each stream, and drive I/O size determination processing, finds completion requirement time when preread or destage processing has to be completed by use of the buffer size and the transfer rate determined in each process, and determines priority order of I/O on the basis of the time.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：即使当多个流混合时也保证每个流的传送速率。解决方案：从主计算机进行多流处理所需的磁盘阵列设备执行传输速率识别处理，用于识别传输速率，驱动性能和故障处理时间识别处理，存储每个流的顺序缓冲区的大小确定处理和驱动 I / O尺寸确定处理，通过使用在每个处理中确定的缓冲器大小和传送速率来完成预读或者流水处理时的完成要求时间，并根据时间确定I / O的优先级顺序。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2006072957A Storage device for executing data migration with worm function, storage system and data moving method 有权
标题翻译：用于执行具有WORM功能，存储系统和数据移动方法的数据移动的存储设备
公开(公告)号：JP2006072957A
公开(公告)日：2006-03-16
申请号：JP2004329431
申请日：2004-11-12
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NONAKA YUSUKE , MATSUNAMI NAOTO , NISHIMOTO SATORU , NAKAGAWA YUTAKA
IPC分类号： G06F12/00 , G06F3/06 , G06F13/10 , G06F21/02
摘要： PROBLEM TO BE SOLVED: To realize the migration of data maintaining WORM attributes. SOLUTION: A storage device is connected with a computer system through a network and is provided with a controller and a drive unit including a plurality of logical volumes, and updating inhibition information indicating inclusion of an area assigned an updating inhibition attribute is recorded in at least one of the logical volumes. The controller includes a configuration management part that sets the logical volume assigned the updating inhibition attribute as a logical volume of a migration source and another logical volume as a logical volume of a migration destination and sets the updating inhibition information concerning the logical volume of the migration source in the logical volume of the migration destination, and a migration part that copies data of the logical volume of the migration source to the logical volume of the migration destination after the setting of the updating inhibition information concerning the logical volume of the migration source in the logical volume of the migration destination. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：实现数据维护WORM属性的迁移。解决方案：存储设备通过网络与计算机系统连接，并且设置有控制器和包括多个逻辑卷的驱动单元，并且记录指示包括分配有更新禁止属性的区域的禁止信息被记录在至少一个逻辑卷中。控制器包括配置管理部分，其将分配有更新禁止属性的逻辑卷设置为迁移源的逻辑卷，将另一逻辑卷设置为迁移目的地的逻辑卷，并且设置关于迁移的逻辑卷的更新禁止信息迁移目的地的逻辑卷中的源，以及迁移部分，在迁移源的逻辑卷的更新禁止信息设置之后，将迁移源的逻辑卷的数据复制到迁移目的地的逻辑卷迁移目的地的逻辑卷。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2006040011A Disk array system 有权
标题翻译：磁盘阵列系统
公开(公告)号：JP2006040011A
公开(公告)日：2006-02-09
申请号：JP2004220025
申请日：2004-07-28
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NISHIMOTO SATORU , MATSUNAMI NAOTO , SATO MASAHIKO , BABA HIDEMI
IPC分类号： G06F3/06 , G06F12/08
CPC分类号： G06F11/1076 , G06F12/0866 , G06F2211/1007 , G06F2211/1009 , G06F2211/104
摘要： PROBLEM TO BE SOLVED: To accurately generate an LA, even when out-of-order occurs.
SOLUTION: This disk array system has: a host input/output part performing transmission/reception of data or a control signal to a host connected to the disk array system; a disk input/output part performing transmission/reception of the data or the control signal to a disk; a cache memory temporarily storing the data transferred between the host input/output part and the disk input/output part with a segment configured by a set of a plurality of blocks of prescribed size as a unit; an MPU control operation of a control part by executing a control program; and a cache controller controlling input/output of the data to the cache memory. The host input/output part transfers, transfer information containing the guarantee code of a head block of the segment related to the transfer, to the cache controller.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了精确地生成LA，即使发生乱序。解决方案：该磁盘阵列系统具有：向连接到磁盘阵列系统的主机执行数据发送/接收或控制信号的主机输入/输出部分; 执行将数据或控制信号发送/接收到盘的盘输入/输出部分; 高速缓存存储器，其将由主机输入/输出部分和盘输入/输出部分之间传送的数据暂时存储为由一组规定尺寸的多个块组成的段作为单元; 执行控制程序的控制部的MPU控制动作; 以及控制将数据的输入/输出到高速缓冲存储器的高速缓存控制器。主机输入/输出部分将包含与传送相关的段的头块的保证代码的传送信息传送到缓存控制器。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2003140910A BINARY TRANSLATION METHOD IN VLIW PROCESSOR 审中-公开
公开(公告)号：JP2003140910A
公开(公告)日：2003-05-16
申请号：JP2001338865
申请日：2001-11-05
申请人： HITACHI LTD
发明人： NISHIMOTO SATORU
IPC分类号： G06F9/38 , G06F9/30 , G06F9/45 , G06F9/455
摘要： PROBLEM TO BE SOLVED: To reduce a processing period of a command scheduling in a binary translation on a VLIW processor that needs to avoid competition of resources by software. SOLUTION: In the binary translation, a plurality of commands share the resources such as a write port, and a processor having no function of avoiding stall or competition of pipe lines when the resources compete with each other in execution is used as a host processor. The host processor has a function of detecting only whether the competition of the resources occurs and a resource competition check register for indicating the occurrence of the competition. In scheduling the commands in the binary translation, the commands are actually executed using a resource check function of hardware, thereby checking for the competition of the resources.

5. 发明专利

JPS63263903A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63263903A
公开(公告)日：1988-10-31
申请号：JP9733987
申请日：1987-04-22
申请人： HITACHI LTD
发明人： NISHIMOTO SATORU , SHIMOKAWA RYUSHI , UEDA SEIICHI
IPC分类号： H01L27/04 , H01L21/822 , H01L27/06 , H03F1/00 , H03F3/195 , H03F3/20 , H03F3/213
摘要： PURPOSE:To stabilize the operation of an IC by forming a resistor between one end of undesired parasitic capacitance formed attended with the forming of a load resistance and a power supply path so as to reduce the frequency component leaked to the power supply path via the parasitic capacitance. CONSTITUTION:An emitter of a transistor (TR) Q1 is connected to ground and a resistor R1 acts like a load resistor. An input signal Vin is fed to the base and an amplified output signal Vout is obtained from a collector. One end of the parasitic capacitance C1 is connected to the power supply path Vcc via a resistor R0. Inductances L1, L2 are the inductance of a couple of the power path and the inductance of the leads of the IC. The impedance of the parasitic capacitance C1 varies with the frequency of an output signal Vout and since the resistor R0 is interposed with the power path Vcc, the signal leakage from the collector via the capacitor C1 is reduced.

6. 发明专利

JPS61274421A ANALOG SWITCH 失效
公开(公告)号：JPS61274421A
公开(公告)日：1986-12-04
申请号：JP11417085
申请日：1985-05-29
申请人： HITACHI LTD
发明人： KATO KAZUO , SATO HIDEO , YAMASHITA KENKICHI , NISHIMOTO SATORU
IPC分类号： H03K17/60
摘要： PURPOSE:To obtain the titled switch of a low offset voltage and also a low on-impedance by bringing transistors to an transverse-parallel connection to each other, and making an operating bias current flow to bases separately. CONSTITUTION:Transistor TRs 101 and 102 for constituting an analog switch 100 are brought to the transverse-parallel connection, and to each base, a bias circuit 50 and a switch controlling circuit 150 are connected. When turning on the switch 100, TRs 151, 152 are turned off by a control input terminal 155. As a result, the TRs 101, 102 conduct by a bias current by constant-current sources 51, 52, and a signal source 10 and a load terminal 25 become a conducting state. In this state, the TRs 101 and 102 are brought to the transverse-parallel connection, and a bias current is supplied independently to each base electrode, therefore, on TR is operated as a forward direction TR irrespective of the polarity of the difference voltage of a signal source and a load, and shows a small equivalent on-resistance. In this way, two base bias currents flow to the signal source as a reverse direction operation, and an offset voltage becomes small value.

7. 发明专利

JPS61230505A BROAD BAND AMPLIFIER CIRCUIT 失效
公开(公告)号：JPS61230505A
公开(公告)日：1986-10-14
申请号：JP7096085
申请日：1985-04-05
申请人： HITACHI LTD
发明人： SATO HIDEO , KATO KAZUO , YAMASHITA KENKICHI , NISHIMOTO SATORU
IPC分类号： H03F3/343 , H03F1/30
摘要： PURPOSE:To obtain a broad band amplifier whose temperature drift is corrected by connecting the 2nd voltage current converting circuit having nearly the same temperature characteristic as that of the 1st voltage current converting circuit to the input of a current mirror circuit. CONSTITUTION:In impressing a voltage signal to an input terminal 300, it is converted into a current signal by a resistor 30, the signal is given to a transistor (TR) 40 connected to a diode of the current mirror circuit 4, and a current equal to the current flowing to the TR 40 flows to the connector of a TR 41 being an output of the circuit 4. Since the voltage at an input point of the circuit 4 is a voltage VBE similarly as that of the circuit 1, an output current Ic41 of the circuit 3 is expressed as Ic41=(V300-VBE)/R30, where V300 is a voltage impressed to a terminal 300 and R30 is a resistance value of the resistor 30. Thus, the temperature drift produced in the input current of the circuit 1 is corrected. Since the TR41 is constituted as a common emitter circuit, the TR 41 is not saturated and the range in the input voltage V30 is widened.

8. 发明专利

JPS61228777A AMPLIFIER CIRCUIT 失效
公开(公告)号：JPS61228777A
公开(公告)日：1986-10-11
申请号：JP6892785
申请日：1985-04-03
申请人： HITACHI LTD
发明人： NISHIMOTO SATORU , UEDA SEIICHI , KAMATA YASUHARU , YAMASHITA KENKICHI , KATO KAZUO , SATO HIDEO
IPC分类号： G09G1/00 , H04N5/14
摘要： PURPOSE:To obtain a high output (a high amplifier) signal and to increase easily the integrating degree of a semi-conductor integrating circuit by supplying an input signal evenly to the base of a reference transistor of plural current mirror circuits having a good pairing characteristic and by current-adding the output current. CONSTITUTION:A current amplifier circuit 25 is inserted into and applied for the amplifier circuit and, for example, consists of eight current mirror circuits 25a-25h having the same circuit constitution. Current flow through transistors Q112 and Q113 is controlled by the output voltage of a utilizing circuit 24a and by controlling the base current of transistors Q112-Q115 by the Q113, the base current of a transistor Q116 is also controlled. The Q116 supplies the base current to transistors Q121 and Q122 which constitutes the current mirror circuit. Therefore, the current flow from an output circuit 26 and a line 1a through the Q122 and a resistor R97 is varied corresponding to the output voltage of the utilizing circuit 24. Assuming that the intaking current of one current amplifier circuit 25a is Ia, the current intaken from an output circuit 26 through a line la becomes 8Ia.

9. 发明专利

JP2009230352A Storage capacity extension method and storage system using the method 有权
标题翻译：存储容量扩展方法和使用该方法的存储系统
公开(公告)号：JP2009230352A
公开(公告)日：2009-10-08
申请号：JP2008073605
申请日：2008-03-21
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SHIGA KENTA , NISHIMOTO SATORU
IPC分类号： G06F3/06 , G06F12/00
CPC分类号： G06F3/0665 , G06F3/0607 , G06F3/0629 , G06F3/0644 , G06F3/0689
摘要： PROBLEM TO BE SOLVED: To solve the following problem: when additionally providing a disk drive to a RAID group in each RAID, additionally provided capacity cannot be used until relocation of data ends. SOLUTION: In this storage system, respective real areas of the plurality of disk drives included in the storage system include management units. When a controller of the storage system receives a request for writing in an unused virtual area, the controller allocates the real area of a plurality of first disk drives to the virtual area, distributedly stores the data in the plurality of management units of the allocated real area. When the controller receives a request to additionally provide a second disk drive, the controller distributedly stores the data stored in the plurality of management units of the plurality of first disk drives in the plurality of management units of the plurality of first disk drives and the second disk drive. When the controller receives the request for writing of the data in the unused virtual area, the controller allocates the real areas of the plurality of first disk drives and the second disk drive. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：解决以下问题：当向每个RAID中的RAID组额外提供磁盘驱动器时，在数据重新定位结束之前，额外提供的容量不能使用。解决方案：在该存储系统中，包括在存储系统中的多个磁盘驱动器的实际区域包括管理单元。当存储系统的控制器接收到在未使用的虚拟区域中写入的请求时，控制器将多个第一磁盘驱动器的实际区域分配给虚拟区域，将数据分布式存储在所分配的真实的多个管理单元中区。当控制器接收另外提供第二磁盘驱动器的请求时，控制器将存储在多个第一磁盘驱动器的多个管理单元中的数据分散存储在多个第一磁盘驱动器的多个管理单元中，并且第二磁盘驱动器。当控制器接收到在未使用的虚拟区域中写入数据的请求时，控制器分配多个第一磁盘驱动器和第二磁盘驱动器的实际区域。版权所有（C）2010，JPO＆INPIT

10. 发明专利

JP2007219571A Storage controller and storage system 审中-公开
标题翻译：存储控制器和存储系统
公开(公告)号：JP2007219571A
公开(公告)日：2007-08-30
申请号：JP2006035953
申请日：2006-02-14
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： MANNEN AKIHIRO , NISHIMOTO SATORU , OGAWA JUNJI
IPC分类号： G06F3/06 , G06F11/00
CPC分类号： G06F3/0659 , G06F3/0607 , G06F3/0617 , G06F3/0632 , G06F3/0635 , G06F3/0662 , G06F3/067 , G06F8/65 , G06F8/67
摘要： PROBLEM TO BE SOLVED: To update a program in a storage controller while processing an access request without placing a load on a host computer. SOLUTION: An updating control part 8 is started up in the controller of an updating object, when the program is indicated to be updated from a control terminal 6. The updating control part 8 updates the program stored in a program memory 2A4 or a boot disc 4A, after connecting a host I/F part 2A1 to an access request processing part 2B3 in the other controller 2B by a connection control part 7. When the updating is finished, the updating control part 8 connects again the host I/F part 2A1 to an access request processing part 2A3 by the connection control part 7. The access request processing part 2B3 can process continuously the access request from a host computer 5 in stead of the access request processing part 2A3, because storage contents of respective data memories 2A5, 2B5 are synchronized. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：在处理访问请求而不在主机上负载的情况下更新存储控制器中的程序。解决方案：当从控制终端6指示更新程序时，在更新对象的控制器中启动更新控制部分8.更新控制部分8更新存储在程序存储器2A4中的程序或在通过连接控制部分7将主机I / F部分2A1连接到另一控制器2B中的访问请求处理部分2B3之后的引导盘4A。当更新完成时，更新控制部分8再次连接主机I / F部分2A1连接到连接控制部分7的访问请求处理部分2A3。访问请求处理部分2B3可以由主计算机5代替访问请求处理部分2A3连续地处理访问请求，因为各个数据的存储内容存储器2A5,2B5同步。版权所有（C）2007，JPO＆INPIT

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