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1. 发明专利

JP2000035924A BUS CONTROL METHOD 失效
公开(公告)号：JP2000035924A
公开(公告)日：2000-02-02
申请号：JP13646499
申请日：1999-05-17
申请人： HITACHI LTD
发明人： KONDO NOBUKAZU , KANEKO SEIJI , GENMA HIDEAKI , OKADA TETSUHIKO , KOMORI KAZUHIKO , OKAZAWA KOICHI
IPC分类号： G06F13/362 , G06F13/00 , G06F13/42
摘要： PROBLEM TO BE SOLVED: To provide the control method of a bus capable of improving bus using efficiency by reducing the overheads of data transfer. SOLUTION: A module (master) 100 for performing read access to the module 101 to be a slave requests a bus using right to a bus arbiter by BREQ signals 61 and reports that the next cycle is the last cycle to be used by the master by LC signals 63. Then, when bus use is permitted by BGRANT signals 62, the read access is activated by transferring an address to the slave 101 by using the A/D 50 of a system bus in the next cycle and the bus using right is released. Only in the case of being incapable of receiving the transferred address, the slave 101 asserts RETRY signals 55 two cycles after the transfer cycle of the non-received address. The module 100 which executes transfer two cycles before the cycle in which the RETRY signals 55 are asserted executes the transfer executed two cycles before again.

2. 发明专利

JPH0310128B2 失效
公开(公告)号：JPH0310128B2
公开(公告)日：1991-02-13
申请号：JP2896883
申请日：1983-02-23
申请人： HITACHI LTD
发明人： UCHIUMI KAZUHIKO , KOMORI KAZUHIKO , YAMAMOTO JUNICHI , KIKUTA SHIGEO , ONDA SHIGEO
IPC分类号： H02J1/00 , G06F1/00 , G06F1/26

3. 发明专利

JPH01156834A DIAGNOSING SYSTEM FOR CHECK CIRCUIT 失效
公开(公告)号：JPH01156834A
公开(公告)日：1989-06-20
申请号：JP31583587
申请日：1987-12-14
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： ITO HIROMICHI , SEKI YUKIHIRO , YAMAGAMI HAJIME , MASUKO ATSUSHI , KOBAYASHI HITOSHI , KOBAYASHI SHIGEO , KOMORI KAZUHIKO
IPC分类号： G06F11/08 , G06F12/16
摘要： PURPOSE:To facilitate the diagnosis of an error detecting circuit and an error detecting/correcting circuit of a memory by changing the data or the check information to the wrong value in a write or read state of a memory and supplying the changed data or information to a check circuit to perform the diagnosis of the check circuit. CONSTITUTION:When a writing action is applied to a diagnosing area, a check information changing command signal 4 is transmitted from an address decoder 2. Then a parity bit 6 is inverted by a check information changing circuit 7 and shows the wrong value. The inverted bit 6 is written into a memory 8 together with the write data 10. Thus it is decided that a parity generator 5, the circuit 7 and a parity checker 9 are normal as long as an error detecting signal 12 is transmitted in a read state. As a result, the diagnosis is facilitated for an error detecting circuit and an error detecting/correcting circuit.

4. 发明专利

JPS62214588A REFRESH CONTROL METHOD FOR DYNAMIC MEMORY 失效
公开(公告)号：JPS62214588A
公开(公告)日：1987-09-21
申请号：JP5703686
申请日：1986-03-17
申请人： HITACHI LTD
发明人： ITO MIKIYA , KOBAYASHI SHIGEO , KOMORI KAZUHIKO
IPC分类号： G11C11/406 , G11C11/34
摘要： PURPOSE:To avoid the contention between a memory access request and a refresh request by applying DMA refresh to the refresh control of a dynamic memory only when no refresh is applied by access refresh. CONSTITUTION:When a refresh start section 32 receives a memory access request signal 5 after the reception of a pulse signal 4, the section 32 outputs an access refresh start signal 11 after the end of memory access. The section 32 receives the next signal 4 after a specified time elapses while no signal 5 is outputted after the reception of the signal 4 and when the signal 5 is outputted from a CPU 1, the section 32 outputs an access refresh start signal 11. Further, when the CPU 1 outputs a hold enable signal 6, the start section 32 outputs a DMA refresh start signal. A refresh signal generation section 12 is started by the signal 10 or 11 to execute the refresh of the memory 9. Thus, the contention between the memory access request and the refresh request is avoided and the decrease in the processing capability of the CPU 1 is avoided.

5. 发明专利

JPS62134896A MEMORY CONTROL SYSTEM 失效
公开(公告)号：JPS62134896A
公开(公告)日：1987-06-17
申请号：JP27323285
申请日：1985-12-06
申请人： HITACHI LTD
发明人： KOMORI KAZUHIKO , ITO MIKIYA
IPC分类号： G06F12/00 , G06F12/06 , G11C11/34
摘要： PURPOSE:To prevent a refresh request and an access request from contending with each other in the same memory unit by controlling multiplexers of respective memory units which switch a refresh address and a data access address. CONSTITUTION:Mutually independent memory units 8 and 9 of a memory device 10 are accessed through multiplexers 6 and 7 which select and output refresh addresses from a refresh counter 3 and a refresh address counter 4 and a data access address from a microprocessor unit 2. Those multiplexers 6 and 7 are controlled by a memory control part 5 and when either of the units 8 and 9 is refreshed, the other had its data accesses, thereby preventing a refresh request and a data access request from contending with each other in one memory unit.

6. 发明专利

JP2000035925A BUS CONTROL METHOD 失效
公开(公告)号：JP2000035925A
公开(公告)日：2000-02-02
申请号：JP13646299
申请日：1999-05-17
申请人： HITACHI LTD
发明人： KONDO NOBUKAZU , KANEKO SEIJI , GENMA HIDEAKI , OKADA TETSUHIKO , KOMORI KAZUHIKO , OKAZAWA KOICHI
IPC分类号： G06F13/36 , G06F13/00 , G06F13/362 , G06F13/42
摘要： PROBLEM TO BE SOLVED: To improve the utilizing efficiency of a bus. SOLUTION: A module (master) 100 for performing read access to the module 101 to be a slave requests a bus using right to a bus arbiter by BREQ signals 61 and reports that the next cycle is the last cycle to be used by the master by LC signals 63. Then, when bus use is permitted by BGRANT signals 62, the read access is activated by transferring an address to the slave 101 by using the A/D 50 of a system bus in the next cycle and the bus using right is released. Only in the case of being incapable of receiving the transferred address, the slave 101 asserts RETRY signals 55 two cycles after the transfer cycle of the non-received address. The module 100 which executes transfer two cycles before the cycle in which the RETRY signals 55 are asserted executes the transfer executed two cycles before again.

7. 发明专利

JP2000029827A METHOD FOR CONTROLLING BUS 失效
公开(公告)号：JP2000029827A
公开(公告)日：2000-01-28
申请号：JP13646699
申请日：1999-05-17
申请人： HITACHI LTD
发明人： KONDO NOBUKAZU , KANEKO SEIJI , GENMA HIDEAKI , OKADA TETSUHIKO , KOMORI KAZUHIKO , OKAZAWA KOICHI
IPC分类号： G06F13/42
摘要： PROBLEM TO BE SOLVED: To improve the using efficiency of buses. SOLUTION: A module (master) 100 for executing read access to a module 101 to be a slave requests bus use right to a bus arbiter by a BREQ 61 signal and transmits a message that a succeeding cycle is a final cycle to be used by the master itself by an LC signal 63. When bus use is permitted by a BGRANT signal 62, the master 100 transfers an address to the slave 101 in a succeeding cycle through an A/D 50 to be a system bus to start a read access and release the bus use right. Only when the transferred address can not be received, the slave 101 asserts a RETRY signal 55 two cycles after the transfer cycle of the address which can not be received. The module 100 executing transfer two cycles before the asserted cycle of the RETRY signal 55 reexecutes the transfer executed two cycles before. An address to be transferred can be transferred to a module having prepared the reception of the address only by one cycle.

8. 发明专利

JPH02150927A ERROR CORRECTION SYSTEM 失效
公开(公告)号：JPH02150927A
公开(公告)日：1990-06-11
申请号：JP30215588
申请日：1988-12-01
申请人： HITACHI LTD
发明人： KOBAYASHI SHIGEO , KOMORI KAZUHIKO , KAWASHITA TOMOYOSHI , TASAKA HIROTAKA , TSUCHIDA HACHIO
IPC分类号： G06F11/10
摘要： PURPOSE:To improve the reliability of a error correction system without deteriorating the availability of a memory by deciding the past errors via a comparator and therefore correcting the errors within a range where the error correction rate is kept under a level allowable with the system. CONSTITUTION:In a normal mode a data control part 25 prevents an error detection/correction control part 15 from correcting errors. Thus the part 15 is limited just to detect the errors, and the read data on the reception data read into an A data buffer 14 is set at a B data buffer 21. When an error is detected, the part 25 outputs an error correction grant command 25a with an error correction mode set. Then the data is read again and the data obtained after correction of the error is set at the buffer 14 and a C data buffer 22 respectively. Then the data on both buffers 21 and 22 are compared with each other by a comparator 23. When a burst error having the bits less than the prescribed number of bits is decided, the data on the buffer 22 is handled as the data undergone the correct error correction. While the other data undergo the error processes. Thus it is possible to improve the system reliability without deteriorating the memory availability.

9. 发明专利

JPS59154520A Power source control system 失效
标题翻译：电源控制系统
公开(公告)号：JPS59154520A
公开(公告)日：1984-09-03
申请号：JP2896883
申请日：1983-02-23
申请人： Hitachi Ltd
发明人： UCHIUMI KAZUHIKO , KOMORI KAZUHIKO , YAMAMOTO JIYUNICHI , KIKUTA SHIGEO , ONDA SHIGEO
IPC分类号： H02J1/00 , G06F1/00 , G06F1/26
摘要： PURPOSE: To control a power source efficiently through simple constitution by confirming that power sources of other processors are all turned off on the basis of the contents of a storage circuit when a power-off control instruction is supplied from an input device and supplying a power-off command to a power source disconnecting circuit.
CONSTITUTION: A main data processor 1 sends a polling signal at a specific period to perform transmission; when there is no answer, "0" is set in a register 7 while the power source 13 of a slave data processor 10 is turned off, and when there is an answer, a value other than "0" is set in the register 7. When the power-off control instruction is inputted from the input device 8 of the processor 1 while the processors 1 and 10 are both powered off, the processor 1 refers to the contents of the register 7 at the specific period; when the contents are not "0", processing is caried on normally, and when the contents are "0", the power- off command is supplied to the power-off control circuit 5 to turn off the power source 4 automatically through a power-off signal line 6.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：通过简单的结构，通过确认当从输入设备提供断电控制指令并且提供电源时，基于存储电路的内容关闭其它处理器的电源，从而有效地控制电源 -off命令到电源断开电路。构成：主数据处理器1在特定周期发送轮询信号进行传输; 当没有应答时，在从属数据处理器10的电源13关闭时，在寄存器7中设置“0”，当有答案时，设定“0”以外的值在处理器1和10都断电的情况下，当从处理器1的输入装置8输入断电控制指令时，处理器1在特定周期参考寄存器7的内容; 当内容不为“0”时，正常进行处理，当内容为“0”时，向断电控制电路5提供断电命令，关闭电源4 自动通过断电信号线6。

10. 发明专利

JP2000035944A BUS CONTROLLING METHOD 失效
公开(公告)号：JP2000035944A
公开(公告)日：2000-02-02
申请号：JP13646399
申请日：1999-05-17
申请人： HITACHI LTD
发明人： KONDO NOBUKAZU , KANEKO SEIJI , GENMA HIDEAKI , OKADA TETSUHIKO , KOMORI KAZUHIKO , OKAZAWA KOICHI
IPC分类号： G06F13/362 , G06F13/42
摘要： PROBLEM TO BE SOLVED: To reduce bus occupying time and to improve bus use efficiency by always performing transfer in one cycle per data or address after acquiring the right of use of a bus. SOLUTION: A master 100 which acquires the right of use of a bus communicates data to at least one slave 101, etc., which synchronizes with a clock signal that is common to all modules 100 to 107. The master module 100 continuously executes plural transmission cycles in which data is communicated to the slave 101, etc., after acquiring the right of use of a bus and releases the right of use of a bus after executing the first one cycle of the transfer cycles. And, it conforms if a retry request is issued from at least one of the slave 101, etc., in a preliminarily defined cycle after releasing the right of use of a bus and when the retry request is not received, the next transfer cycle is carried out. It is preferable that a preliminarily defined cycle here is two cycles after releasing the right of use of a bus.

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