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1. 发明专利

JP2001185701A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING IT 失效
公开(公告)号：JP2001185701A
公开(公告)日：2001-07-06
申请号：JP37012599
申请日：1999-12-27
申请人： HITACHI LTD
发明人： YAMADA SATORU , HAYANO KATSUYA , IMAI AKIRA
IPC分类号： H01L21/768 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To improve the process margin at the time of forming the contact hole of a DRAM memory cell. SOLUTION: After a MISFET is formed on the main surface of a semiconductor substrate, an interlayer insulating film is formed and a negative photoresist film is formed on the insulating film. By performing first-stage exposure, the areas F to be irradiated of the photoresist film are irradiated with light by using a phase shift mask formed in a straight line pattern extended in the direction Y in which word lines are extended. Then, by performing second-stage exposure, another areas G to be irradiated of the photoresist film are irradiated with light by using another phase shift mask formed in another straight line pattern extended in the longitudinal direction A of active areas L. Thereafter, a mask is formed by removing the photoresist film from the nonirradiated area and contact holes are formed by performing anisotropic etching.

2. 发明专利

JP2001068398A METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND MASK FABRICATION 失效
公开(公告)号：JP2001068398A
公开(公告)日：2001-03-16
申请号：JP24213699
申请日：1999-08-27
申请人： HITACHI LTD
发明人： HAYANO KATSUYA , HASEGAWA NORIO , IMAI AKIRA , ASAI NAOKO , TSUJIMOTO EIJI , WATANABE KAZUMUNE
IPC分类号： H01L21/027 , G03F1/30 , G03F1/36 , G03F1/68 , G03F1/80 , G03F7/20 , G03F1/08
摘要： PROBLEM TO BE SOLVED: To suppress or prevent a pattern abnormality such as pattern deformation or misalignment of a semiconductor integrated circuit device. SOLUTION: A light intensity is calculated on the basis of mask pattern data DBP and lens aberration data DBL of an exposure apparatus (step 101), its calculated result is compared with a calculated result of a light intensity calculated, based on no lens aberration of the exposure apparatus (step 102), and a pattern exceeding an allowance value among the mask pattern data is corrected so that its value will not exceed the allowable value according to a correction calculated, based on the compared result (step 104). A mask is fabricated with use of mask creation data DBM after the correction, and thereafter the mask is mounted to the exposure apparatus and a predetermined pattern is transferred onto a semiconductor wafer.

3. 发明专利

JPH1117146A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH1117146A
公开(公告)日：1999-01-22
申请号：JP17259597
申请日：1997-06-27
申请人： HITACHI LTD
发明人： ASANO ISAMU , KAWAKITA KEIZO , YAMADA SATORU , NAKAMURA YOSHITAKA , IMAI AKIRA
IPC分类号： H01L21/027 , H01L21/8238 , H01L21/8242 , H01L27/092 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To improve processing accuracy of a lower electrode of an information storage capacitive element of a DRAM. SOLUTION: In a phase shift mask 80A wherein a group of groove patterns 55A for forming a lower electrode of an information storage capacitive element and a frame-shaped light shielding pattern 59A surrounding the group therewith are formed, no region is permitted to exist, in which the space between the outermost peripheral light shielding pattern 55A and the light shielding pattern 59A becomes insufficient for the light resolution. For that purpose, spaces Xw and Yw between the outermost light shielding pattern 55A and the light shielding pattern 59A along directions of X and Y are, respectively, made larger in size than the light resolution (i.e., Xw>Xs, Yw>Ys).

4. 发明专利

JPH1115134A PHOTO MASK AND PATTERN FORMING METHOD USING THE SAME 失效
公开(公告)号：JPH1115134A
公开(公告)日：1999-01-22
申请号：JP16993197
申请日：1997-06-26
申请人： HITACHI LTD
发明人： IMAI AKIRA , HASEGAWA NORIO , HAYANO KATSUYA
IPC分类号： G03F1/30 , G03F1/32 , G03F1/36 , G03F1/68 , H01L21/027 , G03F1/08
摘要： PROBLEM TO BE SOLVED: To make it possible to achieve an improvement in resolution of an isolated pattern and dense patterns by using a same mask, by providing the same mask with functions of a spatial frequency modulated phase shift mask and a half-tone phase shift mask. SOLUTION: A translucent phase shift film 2 and a shielding film 3 are laminated on a glass substrate 1. Exposure light 4, 5 passing through a transparent part in an area 8 of a spatial frequency modulated phase shift mask part have an opposite phase to each other (b). Therefore, the exposure light interfere each other in the neighborhood of both patterns, and result in showing a steeply varying light intensity distribution, which shows an excellent resolution characteristic (c). Further, since exposure light 6 passing through the translucent film 2 in an area 9 of a half tone phase shift mask part has an opposite phase to exposure light 7 passing through the transparent part (b), it acts to suppress the skirt of the light intensity distribution of the exposure light 7 passing through the transparent part, and that enables to obtain a steeply varying light intensity distribution.

5. 发明专利

JPH09283413A EXPOSURE METHOD AND ALIGNER 失效
公开(公告)号：JPH09283413A
公开(公告)日：1997-10-31
申请号：JP9503596
申请日：1996-04-17
申请人： HITACHI LTD
发明人： IMAI AKIRA , OKAZAKI SHINJI
IPC分类号： G03F7/20 , H01L21/027 , H01L21/677 , H01L21/68
摘要： PROBLEM TO BE SOLVED: To eliminate troublesome cleaning for removal of impurity material by using different aligns in a lithography process before the manufacturing process for deposition a material which causes impurity contamination in a substrate and in a lithography process after the deposit manufacturing process. SOLUTION: An isolation region 72 is formed on the surface of a substrate 71, a word line 73 wherein polycrystalline silicon and silicon oxide are deposited is formed, silicon oxide is applied, a side spacer 74 is formed in a side wall of the word line 73 and an n-diffusion layer 75 is formed. Successively, a data line 76 consisting of polycrystalline silicon is formed, and a platinum film is deposited and processed for forming a storage electrode 78. Thereafter, a capacitor insulation film 79 is formed, polycrystalline silicon is applied for forming a plate electrode 80, a wiring 81 is formed and a DRAM is obtained. In this method, an aligner A is used in a lithography process before a process for depositing platinum and an aligner B is used in a lithography process after a process for depositing platinum.

6. 发明专利

JPH0936017A PATTERN FORMING METHOD AND SEMICONDUCTOR MANUFACTURING METHOD USING THE PATTERN FORMING METHOD 失效
公开(公告)号：JPH0936017A
公开(公告)日：1997-02-07
申请号：JP18382695
申请日：1995-07-20
申请人： HITACHI LTD
发明人： HASEGAWA NORIO , TERASAWA TSUNEO , SHIRAISHI HIROSHI , HAYANO KATSUYA , IMAI AKIRA , TANAKA TOSHIHIKO , ASAI NAOKO , OKAZAKI SHINJI
IPC分类号： G03F7/20 , H01L21/027
摘要： PROBLEM TO BE SOLVED: To eliminate the limitation on the manufacturing steps to which this invention is applied and to improve the depth of focus by forming an overcoat film of a thickness greater than a half of the sum of surface step difference of a substrate, focus distribution width in one-exposure field in projection exposure and depth of focus of a desired resolving pattern. SOLUTION: Photoresist 12 is formed on a substrate 11 with a step and a thick overcoat film 13 having flattened surface is formed. The thickness of the overcoat film 13 is greater than a half of the sum of surface step difference of a substrate, focus distribution width in one exposure field in projection exposure and depth of focus of a predetermined resolving pattern. The method can remove the limitation on the manufacturing steps to which the invention is applied can improve effective depth of focus and can improve accuracy of pattern formation.

7. 发明专利

JPH08306621A METHOD OF EXPOSURE, ALIGNER AND MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH08306621A
公开(公告)日：1996-11-22
申请号：JP22372795
申请日：1995-08-31
申请人： HITACHI LTD
发明人： OKAMOTO YOSHIHIKO , TERASAWA TSUNEO , IMAI AKIRA , HASEGAWA NORIO , OKAZAKI SHINJI
IPC分类号： G03F1/30 , G03F1/68 , G03F7/20 , G03F9/00 , H01L21/027 , G03F1/08
摘要： PURPOSE: To prevent the position deviation of an imaging plane when exposure processing is performed by using a phase shift mask constituted by superimposing two masks. CONSTITUTION: A pattern constituted of a light shielding region and a transparent region is formed on a first mask 12a. A phase shift pattern for generating phase difference in transmission light is formed on a second mask 12b. A superimposed mask 12 is constituted by bringing the first mask 12a close to the second mask 12b or bringing the first mask 12a into contact with the second mask 12b in the state that the respective pattern forming surfaces are faced to each other. Before exposure processing is performed by using the superimposed mask 12, the height position of a semiconductor wafer 14 is transferred in the light axis direction, corresponding to the thickness of a mask board of the second mask 12b.

8. 发明专利

JPH0845820A ALIGNMENT ACCURACY INSPECTION METHOD 失效
公开(公告)号：JPH0845820A
公开(公告)日：1996-02-16
申请号：JP17798794
申请日：1994-07-29
申请人： HITACHI LTD , HITACHI CHEMICAL CO LTD
发明人： HATTORI KOJI , TANAKA TOSHIHIKO , IMAI AKIRA , YAMAMOTO JIRO , UENO TAKUMI , ONOZUKA TOSHIHIKO , MORIUCHI NOBORU , SHIRAI SEIICHIRO
IPC分类号： G03F9/00 , H01L21/027 , H01L21/66
摘要： PURPOSE:To inspect the accuracy of alignment without developing a radiation sensitive composition film which is exposed to light by using the change of a film thickness of the radiation sensitive composition due to exposure and measuring the intensity distribution of reflected light of an exposed part and unexposed part adjacent thereto to measure the alignment accuracy of a mask. CONSTITUTION:A region including a backing thin film pattern is exposed to such light that a radiation sensitive composition film 3 hardly brings about the change of a film thickness. The intensity of reflected light is obtained from the function of position on a substrate. Thereby, the intensity distribution of reflected light is obtained. A relative position between the exposure region 5, the film thickness of which is changed, and a backing thin film pattern 2 can be obtained.

9. 发明专利

JPH06120114A PROJECTION EXPOSURE METHOD AND EQUIPMENT 失效
公开(公告)号：JPH06120114A
公开(公告)日：1994-04-28
申请号：JP26718192
申请日：1992-10-06
申请人： HITACHI LTD
发明人： TERASAWA TSUNEO , OKAZAKI SHINJI , FUKUDA HIROSHI , IMAI AKIRA
IPC分类号： G03F7/20 , G03F9/00 , H01L21/027 , H01L21/30
摘要： PURPOSE:To obtain an exposure method and its equipment wherein the resolution is so balanced that all patterns are resolved, when a reticle pattern in which a pattern having periodicity and a pattern having no periodicity mix is transferred on a wafer. CONSTITUTION:A means for obtaining data which show the characteristics of a reticle pattern, and a means 7 for selecting aperture stops 6-1, 6-2 which are arranged in an illumination light source so as to correspond with the data are installed, and the optimum illumination condition for the reticle pattern is realized. The optimum exposure condition is selected by using the data showing the characteristics of a pattern group constituting a pattern to be transferred, so that the pattern transfer wherein the resolution is balanced for all patterns is enabled.

10. 发明专利

JPH06120108A PROJECTION ALIGNMENT METHOD AND EQUIPMENT 失效
公开(公告)号：JPH06120108A
公开(公告)日：1994-04-28
申请号：JP26718292
申请日：1992-10-06
申请人： HITACHI LTD
发明人： TERASAWA TSUNEO , FUKUDA HIROSHI , OKAZAKI SHINJI , IMAI AKIRA , KIMURA SHINICHIRO
IPC分类号： H01L21/30 , H01L21/027
摘要： PURPOSE:To obtain a method and an equipment wherein a circuit pattern having a fine pattern and a comparatively large area is precisely transferred at a high speed. CONSTITUTION:A plurality of exposure optical systems and a plurality of reticles 5, 6 are introduced, and pattern synthesis is performed on a wafer 11. Further exposure conditions of a plurality of the exposure optical systems are suitably changed. Thereby pattern transfer is achieved. The effect that a circuit pattern of large area can be precisely transferred at a high speed is obtained by combining a plurality of patterns without moving and exchanging the reticles.

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