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    • 1. 发明专利
    • SYNCHRONIZATION CONTROL METHOD FOR TERMINAL ADAPTER
    • JP2000101571A
    • 2000-04-07
    • JP26595798
    • 1998-09-21
    • HITACHI LTD
    • SASAHARA KOJIHIRAI MASATO
    • H04L7/00H04L12/02H04M11/00
    • PROBLEM TO BE SOLVED: To normally perform communication in interconnection of terminal adapters between different makes by providing a buffer in the terminal adapter and adjusting a timing between control signals and data signals sent out to an ISDN line and received from the ISDN line matching the opposing terminal adapter. SOLUTION: At the time of transmitting and receiving the control signals and data signals of an ITU-T recommendation V.24 standard, synchronization between the control signals and the data signals is varied. A transmission data buffer 8 and a control signal buffer 11 respectively delay transmission data and the control signals from a V.24 DTE interface 7 corresponding to a delay from a control part 15 and then, send them out to an ISDN frame generation part 9. A reception data buffer 12 and the control signal buffer 14 respectively delay the transmission data and the control signals delivered from an ISDN frame development part 13 corresponding to the delay value from the control part 15 and then, send them out to the V.24 DTE interface 7.
    • 3. 发明专利
    • DUPLICATE RING SYSTEM
    • JPH04192646A
    • 1992-07-10
    • JP31781790
    • 1990-11-26
    • HITACHI LTDHITACHI COMPUTER ENG
    • KURATA MASAMIHIRAI MASATO
    • H04L12/42
    • PURPOSE:To prevent system-down by devising the system such that a reproduction repeater delivers a fault to subordinate nodes without implementing loopback or bypassing on the occurrence of a fault such as power failure so as to allow a ring configuration controller to detect the fault surely when the reproduction repeater and the ring configuration controller are in existence in mixture in the system. CONSTITUTION:Stations ST are connected to transmission lines 2 in duplicate by a line concentrator 1 and connected in a ring by using a ring configuration controller 3 checking the normality of a data to configure the ring, and a reproduction repeater 4 to extend the length of the ring. The reproduction repeater 4 does not implement loopback and bypassing on the occurrence of a fault such as a power failure but allows subordinate devices to detect the fault. Since the ring configuration controller 3 recognizes the fault and eliminate a fault location from the ring through loopback, system-down is prevented, the ring is managed and the fault location is easily found out.
    • 7. 发明专利
    • DIFFERENTIAL AMPLIFIER CIRCUIT
    • JPH01170106A
    • 1989-07-05
    • JP32708487
    • 1987-12-25
    • HITACHI LTDHITACHI COMPUTER ENG
    • HIRAI MASATOKURATA MASAMI
    • H03F3/45
    • PURPOSE:To obtain a differential amplifier circuit in which the balance of both outputs of differential outputs are good by packing circuit elements connecting between the emitters of a pair of transistors to an object physically to the emitters of a pair of the transistors. CONSTITUTION:By connecting between the emitters of a pair of transistors Q1 and Q2 to compose the differential amplifier circuit by means of circuit elements (an R1, an R2 and a C), an amplification degree is controlled. At such a time, the circuit elements (the R1, R2 and C) are packed to the object physically to the emitters of the transistors Q1 and Q2. Then, the floating capacity to a ground to accompany the packing of the circuit elements (the R1, R2 and C) is attached to the object to both emitters. The ground impedances of both emitters are also made equal, and the balance of the impedances between both emitters are made good. Thus, the differential amplifier circuit can be obtained in which the balance of both outputs of the differential outputs are good.
    • 9. 发明专利
    • RELAY CONNECTION SYSTEM
    • JPS6243236A
    • 1987-02-25
    • JP18180785
    • 1985-08-21
    • HITACHI LTDHITACHI COMPUTER ENG
    • HIRAI MASATOKURATA MASAMIYOSHINO RYOZO
    • H04L12/42
    • PURPOSE:To offset the crosstalk produced by a relay circuit with no attachment of an external parts by a relay connection system in a trunk coupling unit of a token ring. CONSTITUTION:The signal A sent from a transmission part 5 of a station 1-1 is transmitted to a reception part 4 of a station 1-2 through relays 5 and 8. While the signal B sent from a transmission part 5 of the station 1-2 is transmitted to the reception part 4 of a station 1-3 through relays 7 and 9. Here the positive side crosstalk C(+) of the signal B is produced to a terminal (c) from a terminal (b) of both relays 6 and 7 respectively. While the negative side crosstalk C(-) of the signal B is produced to a terminal (c) from a terminal (b) of both relays 8 and 9 respectively. Then both crosstalks C(+) and C(-) are added together between relays 6 and 9 as well as relays 7 and 8 through connections 14 and 15 and offset with each other. Thus no crosstalk C of the signal B is produced at the reception part 4 of the station 1-2.
    • 10. 发明专利
    • PHASE LOCK DETECTING CIRCUIT
    • JPS61216524A
    • 1986-09-26
    • JP5584185
    • 1985-03-22
    • HITACHI LTD
    • HIRAI MASATOYOSHINO RYOZO
    • H03L7/113H03L7/089H03L7/095
    • PURPOSE:To set a phase lock detection range and also to set an adaptive frequency range without any adjustment only by varying the setting of a delay time by solving problems of a conventional analog system by employing a digital system. CONSTITUTION:A frequency phase comparator 1 outputs signals D and U according to the phase relation between an input signal and the output of a VCO. Those outputs D and U are ORed and a signal 10 which is delayed by a time (t) is sampled by flip-flops 7 and 8 with the leading edge of the VCO output. When the phase difference between the input signal and VCO output is smaller than the delay time (t), the signal 10 is '0' at a sampling point of time, so signals 11 and 12 are both '0' and the output of an AND circuit 9 is '1', so that is detected as a phase lock state. When the phase difference is larger than the delay time (t), the input signal is sampled to obtain '0', but the output side of the VCO is sampled to detect '1' as the signal 10, which is not detected as the phase lock state. Namely, the range wherein the phase lock state is detected is determined only by the delay time (t).