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1. 发明专利

JPS5832510B2 失效
公开(公告)号：JPS5832510B2
公开(公告)日：1983-07-13
申请号：JP1971475
申请日：1975-02-19
申请人： HITACHI LTD
发明人： AOKI MASAO , TAKAHASHI SUSUMU , MURAI FUMIO , KODERA HIROSHI
IPC分类号： H01L29/80 , H01L21/338 , H01L29/38 , H01L29/812

2. 发明专利

JPS5368570A FORMATION METHOD OF SEMICONDUCTOR EPITAXIAL FILM 失效
公开(公告)号：JPS5368570A
公开(公告)日：1978-06-19
申请号：JP14333876
申请日：1976-12-01
申请人： HITACHI LTD
发明人： WATANABE KIKUO , HIRAO MOTONAO , ASANO TETSUO , AOKI MASAO
IPC分类号： H01L29/80 , C30B25/18 , H01L21/205 , H01L21/338 , H01L29/812 , H01L29/94
摘要： PURPOSE:To make the supply of epitaxial film forming molecules to substrate crystal surface uniform and obtain a grown layer of an even thickness by beforehand making rough the surface of a support jig for placement of a semiconductor crystal substrate.

3. 发明专利

JPS5277898A CRYSTAL GROWTH OF GALLIUM ARSENIDE FROM VAPOR PHASE 失效
公开(公告)号：JPS5277898A
公开(公告)日：1977-06-30
申请号：JP15330875
申请日：1975-12-24
申请人： HITACHI LTD
发明人： HIRAO MOTONAO , KASHIMURA TAKASHI , AOKI MASAO
IPC分类号： C30B25/02 , C30B29/42
摘要： PURPOSE:To obtain gallium arsenide layer of high resistivity quite easily and that for working of high quality continuously.

4. 发明专利

JPS5277584A GROWING CRYSTAL 失效
公开(公告)号：JPS5277584A
公开(公告)日：1977-06-30
申请号：JP15332275
申请日：1975-12-24
申请人： HITACHI LTD
发明人： KASHIMURA TAKASHI , HIRAO MOTONAO , AOKI MASAO
IPC分类号： H01L29/80 , H01L21/205 , H01L21/338 , H01L29/76 , H01L29/812 , H01L33/30
摘要： PURPOSE:To form epi-film with uniform thickness in surface of crystal by forming epi-film by placing dummy wafer which has the same constitution of crystal as substrate.

5. 发明专利

JPS62162360A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS62162360A
公开(公告)日：1987-07-18
申请号：JP348186
申请日：1986-01-13
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MASUDA HIROO , TORIYABE TATSU , AOKI MASAO , KUME HITOSHI , KADOTA HISHIYOU
IPC分类号： H01L27/088 , H01L21/8234 , H01L21/8238 , H01L27/08 , H01L27/092 , H01L29/78
摘要： PURPOSE:To obtain a desired threshold voltage and a high transfer conductance at the same time by controlling the comprehensive impurity concentration of a current passage region in a semiconductor layer to be lower than the comprehensive impurity concentration of other regions in this semiconductor layer. CONSTITUTION:On a P-type Si substrate 1, source and drain regions 2 and 3 composed of an N-type high concentration impurity layer, a gate oxide film 5, and a gate electrode 4 are formed. A low concentration impurity layer 6 of low comprehensive impurity concentration is formed in a current passage region near the surface of the substrate 1. In an FET, an inversion layer near the surface of the substrate 1 which will become a passage of a current has a thickness about 100Angstrom from the surface of the substrate generally. A threshold value of an MOSFET is generally determined by the impurity concentration from the surface of the substrate 1 to the depth of about 1mum. From the above two points, by reducing only the impurity concentration in the region of about 100-300Angstrom of the surface of the substrate 1 (a part where a current flows), an FET which has a large carrier mobility, i.e., a large transfer conductance and a threshold voltage of desired value can be obtained.

6. 发明专利

JPS52146179A SHAPEEPROCESSING METHOD 失效
公开(公告)号：JPS52146179A
公开(公告)日：1977-12-05
申请号：JP6230576
申请日：1976-05-31
申请人： HITACHI LTD
发明人： AOKI MASAO , TAKAHASHI SUSUMU , KODERA HIROSHI
IPC分类号： H01L21/306 , H01L21/302
摘要： PURPOSE:To process to a desired shape a workpiece placed on a substrate, which is formed of a material different from the substrate, by using a peeling method and a side-etching method in combination.

7. 发明专利

JPH0194484A LSI DESIGNING DEVICE 失效
公开(公告)号：JPH0194484A
公开(公告)日：1989-04-13
申请号：JP25148687
申请日：1987-10-07
申请人： HITACHI LTD
发明人： AOKI MASAO , MASUDA HIROO , ITO KIYOO , AOKI MASAKAZU
IPC分类号： G06F17/50 , H01L21/66 , H01L21/8234 , H01L27/08 , H01L27/088
摘要： PURPOSE:To prevent the long-term reliability characteristics of an MOSLSI from deteriorating by incorporating the model of a channel hot carrier HC phenomenon to a circuit simulator, and automatically decide a deteriorated transistor (TR), and automatically outputting the name of the TR. CONSTITUTION:The titled device possesses a data input means, an LSI characteristic simulation means, the long-term reliability deterioration characteristic calculating means of the MOSFET, a deteriorated TR and deteriorated sub- circuit deciding means, and a data output means. A circuit simulator is used for the LSI characteristic simulation means, and the time change of an output signal according to the time change of an input signal and a voltage change at every node is obtained. From this result, the deciding reference characteristics of the deteriorated TR are calculated by the model of the HC phenomenon, compared with the deciding reference value of the deteriorated TR designated by the input data beforehand, and the deteriorated TR or the deteriorated sub-circuit is automatically extracted. Thus, the long-term reliability characteristics of the MOSLSI due to an HC effect can be prevented from deteriorating.

8. 发明专利

JPS62226279A LSI DESIGNING DEVICE 失效
公开(公告)号：JPS62226279A
公开(公告)日：1987-10-05
申请号：JP6833186
申请日：1986-03-28
申请人： HITACHI LTD
发明人： AOKI MASAO , MASUDA HIROO
IPC分类号： G06F17/50
摘要： PURPOSE:To design an LSI in a short time with high efficiency by using a polynomial model in a repetitive loop for the production of an LSI which satisfies the characteristic specifications. CONSTITUTION:A design matrix produced by a desired procedure offers (p) sets of design parameters. A simulator is used in (p) times to obtain (p) sets of LSI characteristics against those (p) sets of parameters. A repetitive loop which corrects the design parameters uses a polynomial/approximate equation and the CPU time of the repetitive loop can be substantially neglected. Thus the CPU time needed for designing can be shortened and therefore the optimum value of the design parameter satisfying the characteristic specifications can be decided in a short time.

9. 发明专利

JPS59163873A Semiconductor device with electrostatic surge protective circuit 失效
标题翻译：带静电防护电路的半导体器件
公开(公告)号：JPS59163873A
公开(公告)日：1984-09-14
申请号：JP3738583
申请日：1983-03-09
申请人： Hitachi Ltd
发明人： MASUDA HIROO , AOKI MASAO , MATSUO HITOSHI , TAKAHASHI SUSUMU
IPC分类号： H01L29/812 , H01L21/338 , H01L27/02 , H01L27/06
CPC分类号： H01L27/0255
摘要： PURPOSE:To form an electrostatic surge protective circuit on a GaAs substrate by shaping two Schottky diodes between an input terminal and an FET connecting terminal through a resistor on the same substrate in a GaAs FET formed on the substrate. CONSTITUTION:An N type impurity layer 2 is formed on a semi-insulating GaAs substrate 1. Metallic films 5, 5' are in ohmic-contact with the impurity layer 2, and connect to a GaAs semiconductor element through an input terminal 3 and a terminal 4. Metallic layers 6, 6' shaping Schottky junctions together with the impurity layer 2 are formed, and grounded through resistors 9, 9'. When high-voltage electrostatic charges are applied to the terminal 3 in an equivalent circuit shown in the diagram, a Schottky junction 7 junction-breaks down, and discharge passing through the resistor 9 breaks down a Schottky junction 7', and the potential of the terminal 4 is clamped. Accordingly, the breakdown of an element is prevented.
摘要翻译：目的：通过在输入端子和FET连接端子之间通过形成在衬底上的GaAs FET中的同一衬底上的电阻器形成两个肖特基二极管，在GaAs衬底上形成静电浪涌保护电路。构成：在半绝缘GaAs衬底1上形成N型杂质层2.金属膜5,5'与杂质层2欧姆接触，并通过输入端子3与GaAs半导体元件连接，形成与杂质层2一起形成肖特基结的金属层6,6'，并通过电阻9,9'接地。当在图中所示的等效电路中将高压静电电荷施加到端子3时，肖特基结7结断裂，并且通过电阻器9的放电会损坏肖特基结7'，并且电位端子4被夹紧。因此，防止元件的击穿。

10. 发明专利

JPS5250270A MOBILITY MEASURING DEVICE 失效
公开(公告)号：JPS5250270A
公开(公告)日：1977-04-22
申请号：JP12533075
申请日：1975-10-20
申请人： HITACHI LTD
发明人： AOKI MASAO , TAKAHASHI SUSUMU , KURONO HIROKAZU , KODERA HIROSHI
IPC分类号： G01P3/42 , G01P3/52
摘要： PURPOSE:Depth distribution of carrier concentration n is obtained by capacityvoltage (C-V) measurment, and depth distribution of specific resistivity rho and Hall mobility muh is obtained by the Hall effect measurement combining the changes of junction depletion layer, whereby the depth distribution of conductivity mobility muc from n and rho may be obtained.

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