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1. 发明专利

JP2014086598A Method of manufacturing semiconductor device, semiconductor device, and photosensitive resin composition 审中-公开
标题翻译：制造半导体器件的方法，半导体器件和光敏树脂组合物
公开(公告)号：JP2014086598A
公开(公告)日：2014-05-12
申请号：JP2012235060
申请日：2012-10-24
申请人： Hitachi Chemical Co Ltd , 日立化成株式会社
发明人： TOBA MASAYA , KURABUCHI KAZUHIKO , NAGOSHI TOSHIMASA
IPC分类号： H01L23/12 , G03F7/004 , G03F7/027 , H01L21/027 , H01L21/56 , H01L23/29 , H01L23/31
CPC分类号： H01L24/97 , H01L21/568 , H01L24/96 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2224/8203 , H01L2924/18162 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device capable of manufacturing efficiently a semiconductor device subjected to rewiring formation while thinning.SOLUTION: In the method of manufacturing a semiconductor device, while performing the sealing of a semiconductor element 3 and the formation of a first insulating layer 4 collectively in a sealing step, the opposite surface S2 of the semiconductor element 3 can be exposed easily in a peeling step. Consequently, when compared with a conventional method of manufacturing a semiconductor device, a semiconductor device 100 subjected to rewiring formation can be manufactured efficiently while thinning.
摘要翻译：要解决的问题：提供一种制造半导体器件的方法，该半导体器件能够有效地制造经过重新布线形成的半导体器件，同时减薄。在制造半导体器件的方法中，在进行半导体元件3的密封和在密封步骤中共同形成第一绝缘层4，在剥离步骤中可以容易地暴露半导体元件3的相对表面S2。因此，与传统的制造半导体器件的方法相比，可以有效地制造经过重新布线形成的半导体器件100，同时变薄。

2. 发明专利

JP2002189896A SYSTEM FOR PROVIDING SEMICONDUCTOR CONSTRUCTION MATERIAL 失效
公开(公告)号：JP2002189896A
公开(公告)日：2002-07-05
申请号：JP2000387126
申请日：2000-12-20
申请人： HITACHI CHEMICAL CO LTD
发明人： YASUDA MASAAKI , SUGAWARA TAKAO , KAGEYAMA AKIRA , KURABUCHI KAZUHIKO , SUZUKI NAOYA
IPC分类号： G06Q30/06 , G06Q50/00 , G06Q50/04 , G06F17/60
摘要： PROBLEM TO BE SOLVED: To provide a system for providing a semiconductor construction material capable of rapidly providing, at a low cost, a semiconductor construction material meeting the characteristic requirements requested from consumers. SOLUTION: In this system 1 for providing the semiconductor construction material, a semiconductor construction material provider side terminal 3 is connected to consumer side terminals through a communication line. On the consumer side terminal 5, a consumer inputs at least one of the specification values of the type, dimension, and material of an entire semiconductor device, at least one of the characteristic requirements of reliability items, and the characteristic requirement values thereof, or selects them from the pre-displayed standard values of the characteristic requirements. On the supplier side terminal 3, a calculation device 7 selects an applicable semiconductor construction material from the accumulated semiconductor construction information based on the inputted or selected signals on the consumer side terminal 5, and displays on the consumer side terminal.

3. 发明专利

JP2017092385A 半導体装置及び半導体装置の製造方法审中-公开
公开(公告)号：JP2017092385A
公开(公告)日：2017-05-25
申请号：JP2015224117
申请日：2015-11-16
申请人：日立化成株式会社 , Hitachi Chemical Co Ltd
发明人： TOBA MASAYA , MITSUKURA KAZUYUKI , KURABUCHI KAZUHIKO , FUKUHARA KIICHI
IPC分类号： H01L23/12 , H01L23/538 , H05K1/11 , H05K3/24 , H05K3/40
摘要：【課題】チップ同士の伝送に優れた高密度の半導体装置を、良好な歩留まり、かつ、低コストで製造できる製造方法を提供することにある。【解決手段】半導体装置の製造方法は、凹部103を備える第1の絶縁層102上に銅ペーストを塗布する塗布工程と、塗布された銅ペーストを焼結処理して第1のシード銅層104を得る焼結処理工程と、得られた第1のシード銅層104上にめっきを施し、第1のめっき銅層105を形成するめっき工程と、第1の絶縁層102と第1のシード銅層104及び第1のめっき銅層105とが平坦化するように、第1の絶縁層102上の第1のシード銅層104及び第1のめっき銅層105を除去する除去工程と、を備える。【選択図】図9

4. 发明专利

JP2017092269A プリント配線板及びその製造方法审中-公开
公开(公告)号：JP2017092269A
公开(公告)日：2017-05-25
申请号：JP2015221176
申请日：2015-11-11
申请人：日立化成株式会社 , Hitachi Chemical Co Ltd
发明人： FUKUZUMI SHIZU , KURABUCHI KAZUHIKO , TAKEKOSHI MASAAKI , NAGOSHI TOSHIMASA
IPC分类号： H05K3/28 , G03F7/027 , G03F7/029
摘要：【課題】プラズマ処理のような特別な工程を経ることなく製造することができ、異種材料、特にアンダーフィル及び封止材の濡れ性に優れる絶縁層を備えるプリント配線板及びその製造方法を提供することを目的とする。【解決手段】基板と当該基板上に設けられた絶縁層とを備え、絶縁層の基板側とは反対側の表面における少なくとも一部の領域に、溝形状を有する凹部3aが線状に1又は2以上で形成されているプリント配線板を提供する。【選択図】図1

5. 发明专利

JP2013251369A Semiconductor device manufacturing method, thermosetting resin composition used therefor and semiconductor device obtained thereby 审中-公开
标题翻译：半导体器件制造方法，其中使用的THERMOSETTING树脂组合物及其获得的半导体器件
公开(公告)号：JP2013251369A
公开(公告)日：2013-12-12
申请号：JP2012124410
申请日：2012-05-31
申请人： Hitachi Chemical Co Ltd , 日立化成株式会社
发明人： KURABUCHI KAZUHIKO , FUJIMOTO DAISUKE , YAMADA KUNPEI , MURAI HIKARI
IPC分类号： H01L23/12 , H01L23/29 , H01L23/31
CPC分类号： H01L24/96 , H01L21/568 , H01L24/97 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2924/18162 , H01L2924/3511 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a wafer level semiconductor device which can achieve thinning and has less warpage and an excellent heat dissipation property efficiently and at low cost; and provide a thermosetting resin composition used for the method.SOLUTION: A semiconductor device manufacturing method comprises: (I) a process of forming a resist pattern on an active face (surface) of a semiconductor element; (II) a process of arranging a passive face (rear face) of the semiconductor element after forming a temporarily fixed layer on a support medium; (III) a process of encapsulating the active face of the semiconductor element and forming a first insulation layer; (IV) a process of separating the support medium and the temporarily fixed layer to expose the passive face; (V) a process of forming in the first insulation layer, an opening which reaches the active face; (VI) a process of forming a seed layer on the first insulation layer; (VII) a process of forming on the seed layer, a resist for circuit formation; (VIII) a process of forming a wiring pattern and removing the resist pattern; (IX) a process of removing the seed layer; (X) a process of forming a second insulation layer on the wiring pattern and forming an opening which reaches the wiring pattern; and (XI) a process of forming external connection terminals.
摘要翻译：要解决的问题：提供一种能够有效且低成本地制造能够实现变薄并且具有较少翘曲和优异的散热性的晶片级半导体器件的制造方法; 并提供用于该方法的热固性树脂组合物。解决方案：半导体器件制造方法包括：（I）在半导体元件的有源面（表面）上形成抗蚀剂图案的工艺; （II）在支撑介质上形成临时固定层之后，配置半导体元件的被动面（背面）的工序; （III）封装半导体元件的有源面并形成第一绝缘层的工艺; （IV）分离支撑介质和临时固定层以暴露被动面的过程; （V）在第一绝缘层中形成到达活性面的开口的工序; （VI）在所述第一绝缘层上形成种子层的工艺; （VII）在种子层上形成电路形成用抗蚀剂的工序; （VIII）形成布线图案并除去抗蚀剂图案的工艺; （IX）去除种子层的过程; （X）在布线图案上形成第二绝缘层并形成到达布线图案的开口的工序; 和（XI）形成外部连接端子的过程。

6. 发明专利

JP2013115171A Printed wiring board, manufacturing method thereof, and thermosetting resin composition 审中-公开
标题翻译：印刷线路板及其制造方法及热固性树脂组合物
公开(公告)号：JP2013115171A
公开(公告)日：2013-06-10
申请号：JP2011258809
申请日：2011-11-28
申请人： Hitachi Chemical Co Ltd , 日立化成株式会社
发明人： KURABUCHI KAZUHIKO , FUKUZUMI SHIZU , NAGOSHI TOSHIMASA , TANAKA YOSHIO
IPC分类号： H05K3/28
摘要： PROBLEM TO BE SOLVED: To provide a method for efficiently manufacturing a printed wiring board including a solder resist having an opening of a desired size and excellent reliability on a surface thereof.SOLUTION: The method for manufacturing the printed wiring board comprises the steps of: (I) forming a first pattern by performing exposure processing and development processing for a first layer composed of a photosensitive resin composition after forming the first layer on the printed wiring board; (II) forming a second layer composed of a thermosetting resin composition on the printed wiring board so as to cover at least a part of the first pattern; (III) thermally curing the second layer; (IV) exposing the first pattern by grinding the second layer via mechanical polishing; and (V) removing the first pattern via desmear treatment and forming the solder resist having the opening composed of a cured material of the thermosetting resin composition and reaching the surface of the printed wiring board.
摘要翻译：解决的问题：提供一种有效地制造包括具有期望尺寸的开口和在其表面上具有优异的可靠性的阻焊剂的印刷线路板的方法。解决方案：印刷电路板的制造方法包括以下步骤：（I）通过对印刷后形成第一层的感光性树脂组合物构成的第一层进行曝光处理和显影处理，形成第一图案接线板; （II）在所述印刷电路板上形成由热固性树脂组合物构成的第二层，以覆盖所述第一图案的至少一部分; （III）热固化第二层; （IV）通过机械抛光研磨第二层来暴露第一图案; 和（V）通过去污处理去除第一图案，并形成具有由热固性树脂组合物的固化材料构成的开口的阻焊剂到达印刷线路板的表面。版权所有（C）2013，JPO＆INPIT

7. 发明专利

JP2014078622A Printed wiring board, manufacturing method of the same, and thermosetting resin composition 审中-公开
标题翻译：印刷线路板及其制造方法和热固性树脂组合物
公开(公告)号：JP2014078622A
公开(公告)日：2014-05-01
申请号：JP2012225933
申请日：2012-10-11
申请人： Hitachi Chemical Co Ltd , 日立化成株式会社
发明人： KURABUCHI KAZUHIKO , MURAI HIKARI , FUJIMOTO DAISUKE , YAMADA KUNPEI , NAGOSHI TOSHIMASA
IPC分类号： H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a method for efficiently manufacturing a printed wiring board which has fine vias on an interlayer insulation layer and achieves excellent reliability.SOLUTION: A manufacturing method of a printed wiring board includes the steps of: forming a seed layer; forming a first pattern formed by a first photosensitive resin composition so as to cover at least a part of the seed layer; forming a first wiring pattern by an electrolytic plating method and then peeling the first pattern by peeling treatment; forming a second pattern formed by a second photosensitive resin composition so as to cover at least a part of the first wiring pattern; forming second wiring patterns 6a, 6b by the electrolytic plating method and then peeling the second pattern by the peeling treatment; removing the seed layer; forming a third layer formed by a thermosetting resin composition so as to cover at least parts of the first and second wiring patterns; thermally curing the third layer; and grinding the third layer to expose at least a part of the second wiring pattern.
摘要翻译：要解决的问题：提供一种有效地制造在层间绝缘层上具有微细通孔的印刷电路板的方法，并获得优异的可靠性。解决方案：印刷电路板的制造方法包括以下步骤：形成种子层; 形成由第一感光性树脂组合物形成的第一图案，以覆盖种子层的至少一部分; 通过电解电镀法形成第一布线图案，然后通过剥离处理剥离第一图案; 形成由第二感光性树脂组合物形成的第二图案，以覆盖第一布线图案的至少一部分; 通过电解电镀法形成第二布线图案6a，6b，然后通过剥离处理剥离第二图案; 去除种子层; 形成由热固性树脂组合物形成的第三层，以便覆盖所述第一和第二布线图案的至少一部分; 热固化第三层; 并研磨第三层以暴露第二布线图案的至少一部分。

8. 发明专利

JP2013135143A Method for manufacturing semiconductor device, semiconductor device obtained by the same, and thermosetting resin composition used for the same 有权
标题翻译：用于制造半导体器件的方法，由其获得的半导体器件和用于其的热固性树脂组合物
公开(公告)号：JP2013135143A
公开(公告)日：2013-07-08
申请号：JP2011285750
申请日：2011-12-27
申请人： Hitachi Chemical Co Ltd , 日立化成株式会社
发明人： FUKUZUMI SHIZU , KURABUCHI KAZUHIKO , NAGOSHI TOSHIMASA , TANAKA YOSHIO
IPC分类号： H01L23/28 , H01L23/12 , H01L25/10 , H01L25/11 , H01L25/18
CPC分类号： H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/01322 , H01L2924/1533 , H01L2924/18161 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a method for efficiently manufacturing a semiconductor device having a via in a sealing resin layer and excellent reliability, a semiconductor device manufactured by this method, and a thermosetting resin composition suited to semiconductor device manufacturing.SOLUTION: A method for manufacturing a semiconductor device comprises the steps of: (I) forming a layer composed of a photosensitive resin composition on a printed-wiring board having a conductor circuit and then forming a pattern by performing exposure processing and development processing on this layer; (II) mounting a semiconductor element on the printed-wiring board; (III) forming a layer composed of a thermosetting resin composition so as to cover the semiconductor element and at least a part of the photosensitive resin composition and then thermally hardening the layer; (IV) exposing a pattern of the photosensitive resin composition by grinding a surface of the layer composed of the thermosetting resin composition; (V) removing the pattern of the photosensitive resin composition by alkali treatment and forming an inter-layer insulating layer composed of a hardened material of the thermosetting resin composition and having an opening reaching a surface of the printed-wiring board; and (VI) forming a conductive metal or a resin in the opening.
摘要翻译：要解决的问题：提供一种在密封树脂层中有效地制造具有通路的半导体器件和可靠性优异的方法，通过该方法制造的半导体器件和适用于半导体器件制造的热固性树脂组合物。方法：用于制造半导体器件的步骤包括以下步骤：（I）在具有导体电路的印刷电路板上形成由感光性树脂组合物构成的层，然后通过对该层进行曝光处理和显影处理而形成图案; （II）将半导体元件安装在印刷电路板上; （III）形成由热固性树脂组合物构成的层，以覆盖半导体元件和至少一部分感光性树脂组合物，然后热固化该层; （IV）通过研磨由热固性树脂组合物构成的层的表面来曝光感光性树脂组合物的图案; （V）通过碱处理除去感光性树脂组合物的图案，并形成由热固性树脂组合物的硬化材料构成的层间绝缘层，并且具有到达印刷电路板的表面的开口; 和（VI）在开口中形成导电金属或树脂。

9. 发明专利

JP2013058576A Semiconductor package wiring board 审中-公开
标题翻译：半导体包装接线板
公开(公告)号：JP2013058576A
公开(公告)日：2013-03-28
申请号：JP2011195513
申请日：2011-09-07
申请人： Hitachi Chemical Co Ltd , 日立化成株式会社
发明人： TAKEKOSHI MASAAKI , KURABUCHI KAZUHIKO , MIYATAKE MASATO , TSUCHIKAWA SHINJI , OGAWA NOBUYUKI
IPC分类号： H01L23/14 , H05K1/14
CPC分类号： H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor package wiring board which can reduce warp of a semiconductor package due to a temperature change in an use environment or at the time of reflow mounting, and improve temperature cycle resistance of a solder connection part between the semiconductor package and a mounting substrate even when the semiconductor package is thinned.SOLUTION: A semiconductor package wiring board 5 to which a semiconductor element 4 is connected and which is connected to a mounting substrate 2, comprises: a core layer 11 including at least an interlayer insulation layer 14 and a wiring layer 15 formed on a surface of the interlayer insulation layer 14; and an electrode pad 22 electrically and mechanically connected to the mounting substrate 2 via solder bumps 3. The semiconductor package wiring board 5 includes a stress relaxation layer 21 arranged closer to the core layer side than the electrode pad 22 and contacting the electrode pad 22. An average heat expansion coefficient of the interlayer insulation layer 14 of the core layer 11 in a plane direction at 25°C-165°C is not greater than 5.5×10/°C, and an elastic modulus of the stress relaxation layer 21 at 25°C is not greater than 2.5 GPa.
摘要翻译：要解决的问题：提供一种半导体封装布线板，其能够降低由于使用环境中的温度变化或回流安装时的半导体封装的翘曲，并且提高焊料连接部的耐温循环性即使半导体封装变薄，半导体封装和安装基板之间也是如此。解决方案：连接有半导体元件4并连接到安装基板2的半导体封装布线板5包括：至少包括层间绝缘层14和布线层15的芯层11，形成在层间绝缘层14的表面; 电极焊盘22通过焊锡凸块3电气机械地连接到安装基板2.半导体封装布线板5包括布置在比电极焊盘22更靠近芯层侧并与电极焊盘22接触的应力松弛层21。核心层11的层间绝缘层14在25℃〜165℃的平面方向的平均热膨胀系数为5.5×10 -6以下， ℃，应力松弛层21在25℃下的弹性模量不大于2.5GPa。版权所有（C）2013，JPO＆INPIT

10. 发明专利

JP2019091840A 配線層の製造方法並びにシード層の形成方法审中-公开
公开(公告)号：JP2019091840A
公开(公告)日：2019-06-13
申请号：JP2017220740
申请日：2017-11-16
申请人： HITACHI CHEMICAL CO LTD
发明人： TOBA MASAYA , KURABUCHI KAZUHIKO , MINEGISHI TOMONORI , MITSUKURA KAZUYUKI , ABE SHINICHIRO
IPC分类号： H05K3/18 , H01L23/12
摘要：【課題】従来と比較して効率的に配線層を製造できる方法を提供する。【解決手段】本開示は配線層の製造方法に関する。この製造方法は、(A)絶縁材料層を支持基板上に形成する工程と、(B)酸素の存在下、絶縁材料層の表面に対して紫外線を照射する工程と、(C)1×10−5〜100×10−5mol/m2の触媒を絶縁材料層の表面に吸着させる工程と、(D)無電解めっきによってシード層を絶縁材料層の表面に形成する工程と、(E)レジストパターンをシード層の表面上に形成する工程と、(F)シード層の表面であってレジストパターンから露出している領域に、電解めっきによって金属層を形成する工程と、(G)レジストパターンを除去する工程と、(H)レジストパターンの除去によって露出したシード層及び当該シード層と絶縁材料層との間の触媒を除去する工程とをこの順序で含む。【選択図】図2

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