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1. 发明专利

JP2007221066A Semiconductor device, and method of manufacturing semiconductor device 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：JP2007221066A
公开(公告)日：2007-08-30
申请号：JP2006042921
申请日：2006-02-20
申请人： Fujitsu Ltd , Tokyo Institute Of Technology , 国立大学法人東京工業大学 , 富士通株式会社
发明人： SUSHIL K SINGH , ISHIHARA HIROSHI , MARUYAMA KENJI , KONDO MASAO , SATO KEISUKE
IPC分类号： H01L21/8246 , H01L27/105
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device having a microfabricated ferroelectric capacitor.
SOLUTION: The method is for manufacturing the semiconductor device which has a ferroelectric capacitor including a ferroelectric layer. The method comprises a process of forming the ferroelectric layer on a first electrode on a substrate, and a process of forming a second electrode on the ferroelectric layer. The process of forming the ferroelectric layer comprises a first process of forming, by a sol-gel method, the ferroelectric layer which contains BiFeO
3 as a main component, and to which Mn is added so that a composition may be BiFe
1 -x Mn
x O
3 (0.02
摘要翻译：解决的问题：提供一种制造具有微细铁电电容器的半导体器件的方法。解决方案：该方法用于制造具有包含铁电层的铁电电容器的半导体器件。该方法包括在基板上的第一电极上形成铁电层的工艺，以及在铁电层上形成第二电极的工艺。形成铁电体层的工序包括通过溶胶 - 凝胶法形成含有BiFeO 3 SBS作为主要成分的强电介质层的第一工序，添加Mn使其成分可以是BiFe -x Mn O 3 （0.02

2. 发明专利

JP2009230835A Ferroelectric memory 审中-公开
标题翻译：电磁记忆
公开(公告)号：JP2009230835A
公开(公告)日：2009-10-08
申请号：JP2008078090
申请日：2008-03-25
申请人： Fujitsu Ltd , Tokyo Institute Of Technology , 国立大学法人東京工業大学 , 富士通株式会社
发明人： MARUYAMA KENJI , KAWASHIMA SHOICHIRO , HOKO HIROSANE , ISHIHARA HIROSHI
IPC分类号： G11C11/22 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To prevent reduction of a read margin of data held in a ferroelectric memory cell.
SOLUTION: A ferroelectric transistor has a ferroelectric film at a gate insulation film, one side of source/drain is connected to a plate line, the other side of source/drain and a well are connected to a connection node, and a gate is connected to a drive line. A gate of a selection transistor is connected to a word line, one side of source/drain is connected to a bit line, and the other side of source/drain is connected to the connection node. The plate line and the drive line are connected commonly to a column of memory cells arranged in a first direction. The bit line is connected commonly to the column of the memory cell arranged in a second direction crossing to the first direction. The word line is wired obliquely for the first and the second directions. Memory cells arranged in the first direction and memory cells arranged in the second direction are connected to different word lines each other.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了防止保留在铁电存储单元中的数据的读取余量的减少。解决方案：铁电晶体管在栅极绝缘膜处具有铁电膜，源极/漏极的一侧连接到板极线，源极/漏极的另一侧和阱连接到连接节点，并且门连接到驱动线。选择晶体管的栅极连接到字线，源极/漏极的一侧连接到位线，源极/漏极的另一侧连接到连接节点。板线和驱动线共同连接到沿第一方向排列的一列存储单元。位线共同连接到沿与第一方向交叉的第二方向布置的存储单元的列。字线在第一和第二方向上倾斜地布线。沿第一方向布置的存储单元和沿第二方向布置的存储单元彼此连接到不同的字线。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2009224668A Semiconductor device and manufacturing method therefor 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009224668A
公开(公告)日：2009-10-01
申请号：JP2008069338
申请日：2008-03-18
申请人： Fujitsu Ltd , Tokyo Institute Of Technology , 国立大学法人東京工業大学 , 富士通株式会社
发明人： ISHIHARA HIROSHI , SINGH KUMAR SUSHIL , HOKO HIROSANE , SUGIYAMA YOSHIHIRO
IPC分类号： H01L21/8246 , H01L27/105
摘要： PROBLEM TO BE SOLVED: To actualize high remanent polarization amount, low leak current, and low fatigue degradation, while securing process consistency with a silicon process regarding a semiconductor device and a manufacturing method therefor.
SOLUTION: A ferroelectric material composed of BiFeO
3 having the composition of which the mol concentration in regard to whole of BiCrO
3 is 40-60 mol% and BiCrO
3 , is used as a dielectric film consisting a capacitor.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：在确保与半导体器件的硅工艺的工艺一致性的同时，实现高剩余极化量，低漏电流和低疲劳劣化及其制造方法。＆lt; P＆gt;解决方案：具有组成为BiCrO 3 整体的摩尔浓度为40-60摩尔％的组成的BiFeO 3 的铁电材料和BiCrO SB> 3 用作包括电容器的电介质膜。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2008251907A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008251907A
公开(公告)日：2008-10-16
申请号：JP2007092413
申请日：2007-03-30
申请人： Fujitsu Ltd , Tokyo Institute Of Technology , 国立大学法人東京工業大学 , 富士通株式会社
发明人： SUSIL KUMAR SINGH , ISHIHARA HIROSHI , MARUYAMA KENJI , KONDO MASAO
IPC分类号： H01L21/8246 , H01L21/314 , H01L27/105
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can provide favorable electric characteristics and a high remnant polarization quantity, and its manufacturing method.
SOLUTION: A ferroelectric capacitor 5 is formed on an insulating film 1 formed on or above a silicon substrate or the like. In the ferroelectric capacitor 5, a lower electrode 2 formed on the insulating film 1, a capacitance insulating film 3 formed thereon, and an upper electrode 4 formed thereon are provided. As the capacitance insulating film 3, a Bi
1-Y La
Y Fe
1-X Ni
X O
3 film is formed. The Bi
1-Y La
Y Fe
1-X Ni
X O
3 film is a film composed mainly of BiFeO
3 , and has a La content of 4 mol% to 21 mol%, and a Ni content of >0 mol% and ≤15 mol%. The ferroelectric capacitor having such a structure can provide a high remnant polarization quantity Pr, and simultaneously suppress the leak current I
leak low.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供可以提供有利的电特性和高残留极化量的半导体器件及其制造方法。解决方案：在形成在硅衬底等上或上方的绝缘膜1上形成铁电电容器5。在铁电电容器5中，设置形成在绝缘膜1上的下部电极2，形成在其上的电容绝缘膜3和形成在其上的上部电极4。作为电容绝缘膜3，将Bi 1-Y Y Fe 1-X 形成SB> 3 膜。 Bi 1-Y＆lt; SB＆gt; Y＆lt; SB＆gt; 1＆lt; SB 1-X＆lt; SB＆gt; 膜是主要由BiFeO 3 SB组成的膜，La含量为4mol％〜21mol％，Ni含量> 0mol％，≤15mol％。具有这种结构的铁电电容器可以提供高残留极化量Pr，同时将泄漏电流I 泄漏低。版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP2007115733A Ferroelectric capacitor, ferroelectric memory and manufacturing method of them 审中-公开
标题翻译：电磁电容器，电磁记忆及其制造方法
公开(公告)号：JP2007115733A
公开(公告)日：2007-05-10
申请号：JP2005302611
申请日：2005-10-18
申请人： Fujitsu Ltd , Tokyo Institute Of Technology , 国立大学法人東京工業大学 , 富士通株式会社
发明人： HOKO HIROSANE , TAMURA TETSUO , MARUYAMA KENJI , ISHIHARA HIROSHI , SOZAWA KOUYA , AOKI CHIEKO
IPC分类号： H01L21/8246 , H01L21/316 , H01L27/105
摘要： PROBLEM TO BE SOLVED: To provide a ferroelectric capacitor where leak current does not increase even if a buffer layer is arranged between a ferroelectric film and a semiconductor substrate.
SOLUTION: A first buffer layer formed of an amorphous insulating material is formed on a surface of the semiconductor substrate. A second buffer layer formed of a crystalline insulating material is formed on it. The ferroelectric film formed of a ferroelectric material is formed on it. An electrode is formed on it.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：即使在铁电体膜和半导体基板之间设置缓冲层，也可以提供漏电流不增加的铁电电容器。解决方案：在半导体衬底的表面上形成由非晶绝缘材料形成的第一缓冲层。在其上形成由结晶绝缘材料形成的第二缓冲层。在其上形成由铁电体材料形成的铁电体膜。在其上形成电极。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2006108648A Ferroelectric memory, method of recording multi-value data, and method of reading the multi-value data 有权
标题翻译：微电子存储器，记录多值数据的方法以及读取多值数据的方法
公开(公告)号：JP2006108648A
公开(公告)日：2006-04-20
申请号：JP2005252504
申请日：2005-08-31
申请人： Fujitsu Ltd , Tokyo Institute Of Technology , 国立大学法人東京工業大学 , 富士通株式会社
发明人： ARIMOTO YOSHIHIRO , TAMURA TETSURO , HOKO HIROSANE , AIZAWA KOJI , YAMAGUCHI MASAOMI , NARA YASUO , ISHIHARA HIROSHI , TABUCHI YOSHIAKI , TAKAHASHI NORIHIRO , HASEGAWA SATOSHI
IPC分类号： H01L27/105 , G11C11/22 , H01L21/8246
CPC分类号： G11C11/22 , G11C11/5657 , H01L21/28291 , H01L29/6684 , H01L29/78391
摘要： PROBLEM TO BE SOLVED: To provide a ferroelectric memory capable of multi-value recording.
SOLUTION: The ferroelectric memory comprises a semiconductor substrate including a channel region of a first conductivity type, a gate electrode formed on the semiconductor substrate via a ferroelectric film so as to correspond to the channel region in the semiconductor substrate, and first and second diffusion regions of second conductivity types. The diffusion regions are formed on both sides of the channel region in the semiconductor substrate, respectively. In the ferroelectric film, a first region is formed near the first diffusion region, a second region is formed near the second diffusion region, and a third region is formed at the midpoint between the first and second regions. Polarization is induced separately in the first, second, and third regions.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供能够进行多值记录的铁电存储器。铁电存储器包括：半导体衬底，其包括第一导电类型的沟道区;栅电极，经由铁电体膜形成在半导体衬底上，以对应于半导体衬底中的沟道区;以及第一和/ 第二导电类型的第二扩散区。扩散区分别形成在半导体衬底中的沟道区的两侧。在铁电体膜中，在第一扩散区附近形成第一区域，在第二扩散区域附近形成第二区域，在第一区域和第二区域之间的中点形成第三区域。在第一，第二和第三区域分别诱导极化。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2008078248A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008078248A
公开(公告)日：2008-04-03
申请号：JP2006253569
申请日：2006-09-19
申请人： Fujitsu Ltd , Tokyo Institute Of Technology , 国立大学法人東京工業大学 , 富士通株式会社
发明人： SUSIL KUMAR SINGH , ISHIHARA HIROSHI , MARUYAMA KENJI , KONDO MASAO
IPC分类号： H01L21/8246 , C01G49/00 , H01L27/105
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device with which a high remaining polarization amount can be obtained while obtaining satisfactory electric characteristics, and to provide a manufacturing method thereof.
SOLUTION: A ferroelectric capacitor 5 is formed on an insulating film 1 formed on or above a silicone substrate. A lower electrode 2 formed on the insulating film 1, a capacitance insulating film 3 formed on it and an upper electrode 4 formed on it are arranged on the ferroelectric capacitor 5. A BiFe
1-X Cr
X O
3 film is formed as the capacitance insulating film 3. The BiFe
1-X Cr
X O
3 film is mainly composed of BiFeO
3 , and the content of Cr is 8 mol% or below, or it is preferably 3 to 8 mol%. Namely, Cr of 0.08 mol or below, or preferably 0.03 to 0.08 mol is contained in BiFe
1-X Cr
X O
3 of 1 mol. In the ferroelectric capacitor of such a structure, leakage current I
leak can be suppressed to be low while the high remaining polarization amount Pr is obtained.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够获得令人满意的电特性的同时可获得高剩余极化量的半导体器件，并提供其制造方法。解决方案：在硅树脂基板上形成的绝缘膜1上形成铁电电容器5。形成在绝缘膜1上的下电极2，形成在其上的电容绝缘膜3和形成在其上的上电极4被布置在铁电电容器5上.BiFe 1-X 形成作为电容绝缘膜3的“X”<！ - SIPO - > SB 3 。 3 膜主要由BiFeO 3 SB组成，Cr的含量为8mol％以下，优选为3〜8mol％。即，在1摩尔的BiFe 1-X X O 3 中含有0.08摩尔或更低的Cr，优选0.03至0.08摩尔的Cr 。在这样一种结构的铁电电容器中，可以将高电流剩余极化量Pr得到的泄漏电流I 泄漏抑制得较低。版权所有（C）2008，JPO＆INPIT

8. 发明专利

JP2007214532A Semiconductor element, semiconductor memory using the same, data writing method therefor, data reading method and these manufacturing methods 有权
标题翻译：半导体元件，使用其的半导体存储器，数据写入方法，数据读取方法和这些制造方法
公开(公告)号：JP2007214532A
公开(公告)日：2007-08-23
申请号：JP2006229896
申请日：2006-08-25
申请人： Fujitsu Ltd , Tokyo Institute Of Technology , 国立大学法人東京工業大学 , 富士通株式会社
发明人： ISHIHARA HIROSHI , MARUYAMA KENJI , TAMURA TETSURO , HOKO HIROSANE
IPC分类号： H01L21/8246 , H01L21/8247 , H01L27/105 , H01L29/788 , H01L29/792
CPC分类号： G11C11/22 , H01L21/28291 , H01L27/11585 , H01L27/1159 , H01L29/78391
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor element to be used for a non-volatile semiconductor memory or the like, a semiconductor memory using the semiconductor device, its data writing method, data reading method, and those manufacturing method, capable of achieving the microprocessing and integration of cells with superior storage characteristics of data, and for reducing power consumption. SOLUTION: A p-n junction diode GD with a ferroelectric gate as a semiconductor element is provided with a gate electrode 28 formed on a ferroelectric film 26, an inversion layer forming region 90, where an inversion layer is formed in the polarizing direction of the ferroelectric film 26 on a semiconductor substrate 2 at the lower part of the ferroelectric film 26, a cathode region 62 formed at one of the both sides with the inversion layer formation region 90 interposed, and an anode region 64 formed at the other of the both sides. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种用于非易失性半导体存储器等的半导体元件，使用半导体器件的半导体存储器，其数据写入方法，数据读取方法以及这些制造方法，能够实现具有优越数据存储特性的电池的微处理和集成，并降低功耗。解决方案：具有铁电栅极作为半导体元件的pn结二极管GD设置有形成在强电介质膜26上的栅电极28，反型层形成区域90，其中反射层在偏振方向在铁电体膜26的下部的半导体基板2上形成的强电介质膜26，形成在反转层形成区域90的两侧的一侧形成的阴极区域62和形成在另一方的阳极区域64 双方。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JP2009230834A Ferroelectric memory cell and ferroelectric memory 审中-公开
标题翻译：电磁记忆体和电磁记忆
公开(公告)号：JP2009230834A
公开(公告)日：2009-10-08
申请号：JP2008078089
申请日：2008-03-25
申请人： Fujitsu Ltd , Tokyo Institute Of Technology , 国立大学法人東京工業大学 , 富士通株式会社
发明人： MARUYAMA KENJI , KAWASHIMA SHOICHIRO , HOKO HIROSANE , ISHIHARA HIROSHI
IPC分类号： G11C11/22 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To prevent reduction of read margin of data held in a ferroelectric memory cell.
SOLUTION: A ferroelectric transistor FYR has a ferroelectric film FF at a gate insulation film, one side of source/drain is connected to a read word line RWL, the other side of source/drain is connected to a read bit line RBL, and a well NW is connected to a plate line PL. A gate of a selection transistor STR is connected to a write word line WWL, one side of source/drain is connected to a write bit line WBL, and the other side of source/drain is connected to a gate of the ferroelectric transistor. By performing read operation using the source and the drain of the ferroelectric transistor, during read operation, it can be evaded that voltage is applied to the ferroelectric film constituting a gate insulation film of the ferroelectric transistor, and change of a polarization state of the ferroelectric film can be prevented.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了防止保留在铁电存储单元中的数据的读取余量的减少。解决方案：铁电晶体管FYR在栅极绝缘膜处具有铁电膜FF，源极/漏极的一侧连接到读取字线RWL，源极/漏极的另一侧连接到读取位线RBL 并且井NW连接到板线PL。选择晶体管STR的栅极连接到写入字线WWL，源极/漏极的一侧连接到写入位线WBL，源极/漏极的另一侧连接到铁电晶体管的栅极。通过使用铁电晶体管的源极和漏极进行读取操作，在读取操作期间，可以避免对构成铁电晶体管的栅极绝缘膜的铁电体膜施加电压，并且铁电体的极化状态的变化可以防止电影。版权所有（C）2010，JPO＆INPIT

10. 发明专利

JP2005259224A Memory 审中-公开
标题翻译：记忆
公开(公告)号：JP2005259224A
公开(公告)日：2005-09-22
申请号：JP2004067187
申请日：2004-03-10
申请人： Sanyo Electric Co Ltd , Tokyo Institute Of Technology , 三洋電機株式会社 , 国立大学法人東京工業大学
发明人： ISHIKAWA TORU , ISHIHARA HIROSHI , YAMAMOTO SHUICHIRO
IPC分类号： G11C11/22 , H01L21/8246 , H01L27/105
摘要： PROBLEM TO BE SOLVED: To provide a memory capable of suppressing an erroneous discrimination of data at a readout operation while suppressing an increase of a memory cell size.
SOLUTION: This memory is equipped with; a ferroelectric capacitor couple 3 of a memory cell 1a and a ferroelectric capacitor couple 3 of a memory cell 1b respectively having two ferroelectric capacitors 3a and 3b storing data "1" or "0" by means of polarizing to the reverse direction of each other; and field effect transistors 2 including gate electrodes 2a to which both ferroelectric capacitor couples 3 for the memory cell 1a and memory cell 1b are connected.
COPYRIGHT: (C)2005,JPO&NCIPI

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