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1. 发明专利

JPS5757269A Compensating circuit for lane strip 失效
标题翻译：电梯线补偿电路
公开(公告)号：JPS5757269A
公开(公告)日：1982-04-06
申请号：JP13332980
申请日：1980-09-25
申请人： Fujitsu Ltd , Senaa Kk
发明人： IWAMURA KAZUHISA , NAGAO KATSUYUKI , SEKIGUCHI FUKUNORI
IPC分类号： G01S5/10 , G01S1/30
CPC分类号： G01S1/30
摘要： PURPOSE:To obtain correct zone lane display at all times in a decometer of a receiver, by generating carry up or carry down pulses by sensing the lane slip when it occurs. CONSTITUTION:A decometer signal from the receiver is applied to the decometer 11, and the % lane value is displayed. The contents of the decometer 11 is digitized through an A/D converter 11A, sampled in a sampling circuit 16 together with the contents of a zone lane counter 14, and written in a data memory circuit 17. The data written in the data memory circuit 17 is processed in a folding circuit 18, written in a memory circuit 19, averaged in an averaging circuit 20, and inputted into a data difference judging circuit 21. The data difference judging circuit 21 senses the lane slip in the decometer 11, generates the carry up or down pulses, and compensates the lane value in the zone lane counter 14.
摘要翻译：目的：为了在接收机的计重器中始终获得正确的区域通道显示，通过在发生通道时检测车道滑行来产生携带或进位脉冲。构成：将来自接收机的计数器信号应用于计数器11，并显示％通道值。计数器11的内容通过A / D转换器11A进行数字化，A / D转换器11A与采样电路16一起与区域通道计数器14的内容一起采样，并写入数据存储电路17.写入数据存储电路 17在折叠电路18中进行处理，写入存储电路19中，在平均电路20中进行平均处理，并输入到数据差分判定电路21.数据差分判定电路21检测计时器11中的车道滑动，携带或下降脉冲，并补偿区域通道计数器14中的通道值。

2. 发明专利

JPS5928871B2 JPS5928871B2 - 失效
公开(公告)号：JPS5928871B2
公开(公告)日：1984-07-16
申请号：JP13332980
申请日：1980-09-25
申请人： Fujitsu Kk , Senaa Kk
发明人： IWAMURA KAZUHISA , NAGAO KATSUYUKI , SEKIGUCHI FUKUNORI
IPC分类号： G01S5/10 , G01S1/30
CPC分类号： G01S1/30

3. 发明专利

JPS5947603A Microcomputer applied device 失效
标题翻译： MICROCOMPUTER应用器件
公开(公告)号：JPS5947603A
公开(公告)日：1984-03-17
申请号：JP15751782
申请日：1982-09-10
申请人： Fujitsu Ltd
发明人： NAGAO KATSUYUKI , IWAMURA KAZUHISA
IPC分类号： G05B9/02 , G06F11/00
CPC分类号： G06F11/00
摘要： PURPOSE:To recover automatically the stop of output for an electronic device, by detecting a hit of the output due to the break of a power supply of the electronic device having a microcomputer and then controlling the microcomputer which controls said electronic device. CONSTITUTION:A synthesizer 8' consists of a synthesizer circuit 5 containing a microcomputer 4, and the output of the synthesizer 8' delivers the prescribed phase gain, etc. via a phase control detecting circuit 14. If a power supply 7 has a hit, the set information stored in a RAM3 within the computer 4 is erased. Thus the output of the synthesizer 8' is stopped. A detecting circuit 9' detects this output stop of the synthesizer 8' and then applies the signal break information to a microcomputer 6. When the hit of the power supply 7 is recovered, the computer 6 delivers a control signal at a time point of the hit by the information of the circuit 9'. Thus the computer 4 is controlled to set again the circuit 5. In such a way, the output stop of an electronic device can be recovered automatically.
摘要翻译：目的：通过检测由于具有微计算机的电子设备的电源断开而导致的输出命中，然后控制控制所述电子设备的微型计算机，自动恢复电子设备的输出停止。构成：合成器8'由包含微型计算机4的合成器电路5组成，合成器8'的输出通过相位控制检测电路14输出规定的相位增益等。如果电源7有击打，存储在计算机4内的RAM3中的集合信息被擦除。因此合成器8'的输出停止。检测电路9'检测合成器8'的输出停止，然后将信号中断信息施加到微型计算机6.当电源7的命中恢复时，计算机6在时间点撞击电路9'的信息。因此，控制计算机4再次设置电路5.以这种方式，可以自动恢复电子设备的输出停止。

4. 发明专利

JPS585788A POWER SOURCE UNIT FOR DRIVING FLUORESCENT INDICATOR TUBE 失效
公开(公告)号：JPS585788A
公开(公告)日：1983-01-13
申请号：JP10410281
申请日：1981-07-03
申请人： FUJITSU LTD
发明人： IWAMURA KAZUHISA , NAGAO KATSUYUKI
IPC分类号： G09G3/12

5. 发明专利

JPH0248757A DATA COMMUNICATION SYSTEM 失效
公开(公告)号：JPH0248757A
公开(公告)日：1990-02-19
申请号：JP19958588
申请日：1988-08-10
申请人： FUJITSU LTD
发明人： NAGAO KATSUYUKI , MAEDA KEIZO
IPC分类号： G06F13/28 , G06F13/00
摘要： PURPOSE:To surely stop a DMAC so that restoring processing can be performed without delay even in the case of high speed transfer or in the case when a bus was not released by stopping the DMAC forcedly by detecting that DMA transfer is not performed within a time constant period. CONSTITUTION:A hardware timer circuit 43 is operated at every DMA transfer period by using a fact that a DMA (Direct Memory Access) response from a DMA controller (DMAC) 42 corresponds to the actual DMA transfer. When the DMA transfer is not performed within a time constant, the DMAC 42 is stopped forcedly, and the DMAC 42 and the hardware timer circuit 43 are initialized. Thus, since time supervision is performed regardless of a CPU cycle, the time supervision can be surely performed so that the DMAC can be stopped even in the case of the high speed transfer with no CPU cycle and in the case when the DMAC 42 does not release the bus for some reason, and besides, the CPU cycle need not be strictly supervised, and the restoring processing can be performed without delay.

6. 发明专利

JPS59157704A Initializing system 失效
标题翻译：初始化系统
公开(公告)号：JPS59157704A
公开(公告)日：1984-09-07
申请号：JP3099983
申请日：1983-02-28
申请人： Fujitsu Ltd
发明人： NAGAO KATSUYUKI , IWAMURA KAZUHISA
IPC分类号： G05B9/03 , G05B7/02 , G06F11/16 , G06F11/20
CPC分类号： G06F11/16
摘要： PURPOSE:To simplify a setting operation by detecting the power supply in the other system at a power-on time to initialize one system as a current or stand- by system. CONSTITUTION:If a power source 14 of the first system is turned on when power sources of both systems are not turned on yet, a value (0V) of VCC in the second system is detected by an input port 15, and a CPU11 is initialized as a current CPU, and the control is transferred to a next processing 1, and the CPU11 executes operations as the current CPU. Meanwhile, if the power source 14 of the first system is turned on when a power source 24 of the second system is already turned on, the input port 15 detects a value (+5V) of VCC of the second system, and the CPU11 is initialized as a stand-by CPU, and the control is transferred to a next processing 1', and the CPU11 executes operations as the stand-by CPU.
摘要翻译：目的：通过在通电时检测其他系统的电源来简化设置操作，以便将一个系统初始化为当前系统或独立系统。构成：如果两个系统的电源尚未接通，则第一系统的电源14接通，则由输入端口15检测第二系统中的VCC值（0V），CPU11被初始化作为当前CPU，并且控制被转移到下一个处理1，并且CPU11执行作为当前CPU的操作。同时，当第二系统的电源24已经接通时，如果第一系统的电源14接通，则输入端口15检测第二系统的VCC值（+ 5V），CPU11为被初始化为备用CPU，并且控制被转移到下一个处理1'，并且CPU11执行作为待机CPU的操作。

7. 发明专利

JPS5849023A DEVICE FOR HOLDING WIRED CABLE IN DRAWER TYPE ELECTRONIC CIRCUIT UNIT CONTAINING TRESTLE 失效
公开(公告)号：JPS5849023A
公开(公告)日：1983-03-23
申请号：JP14546481
申请日：1981-09-17
申请人： FUJITSU LTD
发明人： IWAMURA KAZUHISA , OOHASHI WATARU , NAGAO KATSUYUKI , WASHINO HIROYUKI
IPC分类号： B65H75/34 , H02G11/00

8. 发明专利

JPH0128951B2 失效
公开(公告)号：JPH0128951B2
公开(公告)日：1989-06-06
申请号：JP10410281
申请日：1981-07-03
申请人： FUJITSU LTD
发明人： IWAMURA KAZUHISA , NAGAO KATSUYUKI
IPC分类号： G09G3/12

9. 发明专利

JPS6331819B2 失效
公开(公告)号：JPS6331819B2
公开(公告)日：1988-06-27
申请号：JP4733382
申请日：1982-03-26
申请人： FUJITSU LTD
发明人： NAGAO KATSUYUKI , IWAMURA KAZUHISA
IPC分类号： G06F11/30 , G06F11/00 , G06F11/16 , G06F11/20 , G06F15/16 , G06F15/177

10. 发明专利

JPS62131622A PROGRAMMABLE VARIABLE WAVELENGTH OSCILLATOR 失效
公开(公告)号：JPS62131622A
公开(公告)日：1987-06-13
申请号：JP27307685
申请日：1985-12-03
申请人： FUJITSU LTD
发明人： NAGAO KATSUYUKI
IPC分类号： H03K3/03 , G06F1/08 , H03K3/78 , H03K23/66
摘要： PURPOSE:To obtain a desired pattern signal with simple constitution by providing a storage section storing a pattern signal having plural wavelength changes to a high-order address and a resistance value signal corresponding to each pattern to a low-order address and a register designating a desired pattern for an RC oscillator. CONSTITUTION:The RC oscillator is provided with a ROM 7 storing a pattern signal having plural wavelength changes to its high-order address and a resistance value signal of each pattern signal to its low-address respectively, a register 9 designating a desired pattern signal from the plural pattern signals, a clock generator 10 being a means reading the resistance value signal of the designated pattern in time series and a counter 8 counting a clock signal additionally. Thus, a signal having the same waveform as the designated waveform by a pattern selection data path is oscillated.

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