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1. 发明专利

JP2000078142A Data transfer device 有权
标题翻译：数据传输设备
公开(公告)号：JP2000078142A
公开(公告)日：2000-03-14
申请号：JP24210998
申请日：1998-08-27
申请人： Fujitsu Ltd , Hitachi Ltd , Nec Corp , Nippon Telegr & Teleph Corp , Oki Electric Ind Co Ltd , 富士通株式会社 , 日本電信電話株式会社 , 日本電気株式会社 , 株式会社日立製作所 , 沖電気工業株式会社
发明人： SATO AKISHI , DOI YUKIHIRO , MIZUNO HIROYASU , KASAHARA HIROAKI , KOBAYASHI TAKAFUMI
IPC分类号： H04L29/08 , H04L12/28 , H04L12/803 , H04L12/951 , H04Q3/00
摘要： PROBLEM TO BE SOLVED: To process the lines of different speeds through the same device by providing (n) pairs of up and down m/n MHz lines between a line corresponding part for housing the line of m MHz and a line interface part for housing the line of m MHz or m/n MHz. SOLUTION: A 600 MHz line corresponding part 20 houses lines 1 and 10 of 600 MHz. A 600 MHz line interface part 30 or 150 MHz line interface azimuths 14-a to 14-d house lines 5 and 6 of 600 MHz or lines 18-a to 18-d and 19-a to 19-d of 150 MHz. Concerning this device, four pairs of up and down lines 3a-3d and 8a-8d or lines 13-a to 13-d and 15-a to 15-d of 150 MHz are provided between the 600 MHz line corresponding part 20 and the 600 MHz line interface part 30 or 150 MHz line interface part azimuths 14-a to 14-d.
摘要翻译：要解决的问题：通过在用于容纳mMHz线的线对应部分和用于容纳mMHz的线路接口部分的线对应部分之间提供（n）对上下m / nMHz线，来处理通过相同装置的不同速度的线 m MHz或m / n MHz的线路。解决方案：600MHz线对应部分20容纳600MHz的线路1和10。 600MHz线路接口部分30或150MHz线路接口方位14-a至14-d的600MHz的线路5和6或者线路18-a至18-d和19-a至19-d的150MHz。关于该装置，在600MHz线路对应部分20和第二线路对应部分20之间提供四对上下线3a-3d和8a-8d或150MHz的线13-a至13-d和15-a至15-d 600MHz线路接口部分30或150MHz线路接口部分方位14-a至14-d。

2. 发明专利

JP2014127890A Radio terminal, management server and radio communication system using the same 有权
标题翻译：无线电终端，管理服务器和无线电通信系统
公开(公告)号：JP2014127890A
公开(公告)日：2014-07-07
申请号：JP2012283908
申请日：2012-12-27
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SAKURAI YOSHIKI , MAZAWA SHIRO , KASAHARA HIROAKI , HAYAMA MASAO
IPC分类号： H04W48/16 , H04W48/18 , H04W64/00 , H04W88/06
CPC分类号： H04W28/0289 , H04W28/06 , H04W48/18 , H04W72/1289 , H04W88/06 , H04W88/10
摘要： PROBLEM TO BE SOLVED: To improve the QoE of a user with the reduction of a reconnection frequency of a radio terminal, when the radio terminal connects to one radio communication method among a plurality of radio communication methods in an area in which a plurality of radio systems that use different radio communication methods exist.SOLUTION: When the plurality of radio systems having different service areas exist, the radio terminal includes a function of collecting the histories of application information and position information to transmit to a priority table management server, and based on the information, the priority table management server includes a function of generates a priority table to transmit the information to the radio terminal. Based on the information, the radio terminal selects a connection destination.
摘要翻译：要解决的问题：为了在降低无线终端的重新连接频率的情况下提高用户的QoE，当无线终端在多个无线电通信方法中连接多个无线电通信方法时，在多个无线电存在使用不同无线电通信方式的系统。解决方案：当存在具有不同服务区的多个无线电系统时，无线终端包括收集应用信息和位置信息的历史以发送给优先级表管理服务器的功能，并且基于在该信息上，优先级表管理服务器包括生成将该信息发送到无线终端的优先级表的功能。基于该信息，无线终端选择连接目的地。

3. 发明专利

JPS60111767A LASER SOLDERING METHOD 失效
公开(公告)号：JPS60111767A
公开(公告)日：1985-06-18
申请号：JP21790583
申请日：1983-11-21
申请人： OKI ELECTRIC IND CO LTD
发明人： TAYAMA MASASHI , KASAHARA HIROAKI
IPC分类号： H05K3/34 , B23K1/005
摘要： PURPOSE:To perform satisfactory and stable connection of mounting parts by determining the space between a condenser lens and leads in such a way that the beam diameter of laser light has the diameter equal to the diameter of the lead width of the mounting parts and irradiating the soldering parts of the leads over the entire part. CONSTITUTION:Such a condenser lens 8 with which the beam diameter phi of laser light is made equal to the width (d) of the leads 11 of a mounting part is selected and the space between the leads 11 and the lens 8 is so determined that the beam diameter phi of the laser light is made equal to the width (d) of the leads 11 at the distance f-h shorter than the focal length (f) of the lens 8 in a laser soldering method for soldering the mounting part to a packaging board 10 by the laser light. The laser light is then irradiated to the soldering parts of the leads 11 over the entire surface thereof, thereby soldering the mounting part and the board 10.

4. 发明专利

JP2003198611A TRAFFIC SHAPER AND BANDWIDTH CONTROL EQUIPMENT 审中-公开
公开(公告)号：JP2003198611A
公开(公告)日：2003-07-11
申请号：JP2001399076
申请日：2001-12-28
申请人： HITACHI LTD
发明人： TAKASE MASAYOSHI , MORIWAKI NORIHIKO , WADA MITSUHIRO , KASAHARA HIROAKI , OZAKI NAOHIKO
IPC分类号： H04L12/863 , H04L12/815 , H04L12/819 , H04L12/873 , H04Q11/04 , H04L12/56
摘要： PROBLEM TO BE SOLVED: To provide a traffic shaper which assures the lowest guarantee bandwidth of each traffic, and can transfer a variable length packet by using effectively an empty bandwidth of a communication circuit. SOLUTION: The traffic shaper is provided with a bandwidth control unit 40 constituted of a plurality of leaky buckets 41-1 to 41-n which are prepared corresponding to buffer memories 20-1 to 20-n, and an output queue determining part 43 for specifying the buffer memory to read a packet, on the basis of a difference value between a level count value outputted from each of the leaky buckets and a threshold value corresponding to the previously indicated lowest guarantee bandwidth. Each of the leaky buckets 41 is provided with a level counter 416 which decreases a count value at a constant speed, and level raising means 411-417 which increase a count value of the level counter by the amount being in proportion to a packet length when the packet is read from the corresponding buffer memory. COPYRIGHT: (C)2003,JPO

5. 发明专利

JP2001057561A COMMON BUFFER TYPE PACKET SHAPER 失效
公开(公告)号：JP2001057561A
公开(公告)日：2001-02-27
申请号：JP23213899
申请日：1999-08-19
申请人： HITACHI LTD
发明人： MORIWAKI NORIHIKO , OZAKI NAOHIKO , WADA MITSUHIRO , KASAHARA HIROAKI , ENDO NOBORU
IPC分类号： H04L12/863 , H04L12/28 , H04L12/815 , H04L12/879 , H04L12/931 , H04L12/56
摘要： PROBLEM TO BE SOLVED: To provide a common buffer type packet shaper means that can cope with a high-speed channel by decreasing a packet read time interval for each flow such as a quality class configured in a common buffer. SOLUTION: In the adderss management for a common buffer, a plurality of output sequence chains having a write adderss register 20 and a read adderss register 30 are assigned to each flow such as quality class. The shaper is provided with a distribution pointer 22 that cyclicly distributes a packet of a corresponding flow to a plurality of output sequence chains to attain pipeline reading through the use of a plurality of the output sequence chains, a write adderss register selection circuit 21, a read pointer 32 that conducts cyclic reading from a plurality of the output sequence chains and a read adderss register selection circuit 31.

6. 发明专利

JP2000307582A FIXED LENGTH PACKET SWITCH 失效
公开(公告)号：JP2000307582A
公开(公告)日：2000-11-02
申请号：JP11758199
申请日：1999-04-26
申请人： NIPPON TELEGRAPH & TELEPHONE , HITACHI LTD
发明人： GENDA KOICHI , UGA MASANORI , KASAHARA HIROAKI , TAKAHASHI MASAMI
IPC分类号： H04L12/28
摘要： PROBLEM TO BE SOLVED: To reduce cost by constituting a switch of k-piecs of the unit fixed length packet switches(PS) of N input/N output and N-pieces of the switch interfaces(SIF) of j-input/j-output, connecting k-pieces of input/output groups of SIF to k-pieces of different PS and connecting the remaining input/output groups to the outer circuits of SIF. SOLUTION: An ATM switch 1 is constituted of the small ATM switches 10-v (v=1-k) of a switch size N×N and switch interface(SIF) parts 20-w (w=1-N). Signal lines 100-wU and 100-wD connect the SIF parts 20-w with an outer circuit and signal lines 200-(w, v)U and 200-(w, v)D connect the small ATM switches 10-v and the SIF parts 20-w. The ATM switch 1 can possess switch capacity which is k-times as much as switch capacity that the small ATM switch 10-v has. Thus, a packet order is guaranteed and the fixed length packet of the non-block of large capacity can be realized.

7. 发明专利

JPH11252086A CELL DEVIDED ATM SWITCH 失效
公开(公告)号：JPH11252086A
公开(公告)日：1999-09-17
申请号：JP4673598
申请日：1998-02-27
申请人： HITACHI LTD
发明人： MORIWAKI NORIHIKO , KASAHARA HIROAKI , OGURI YOZO , MAKIMOTO AKIO
IPC分类号： H04Q3/00 , H04L12/28
摘要： PROBLEM TO BE SOLVED: To compose an ATM switch of a small scale capacitance of an optimum hardware amount while using a same switch element by optimizing the number of required partial cell switches by changing an input link to the partial cell switch of the plural partial cells and an output link from the partial cells to plural cell coupling means in accordance with the requested switch capacitance. SOLUTION: Each partial switch is composed of input highways 8-1-n to 8-8-n (n) is any one of 1 to 4}, a routing tag converting part 11, a cell multiplexing part 12, a control part 4, a cell buffer part 15, a cell separating part 16 and output highways 9-1-n to 9-8-n (n) is any one of 1 to 4}. Routing tags 18R-1 to 18R-8 showing the output routes of the switches from the respective input highways are inputted to the partial cell switches. When the switch scale is 8×8 for example, any value of 1 to 8 is applied in this area and when the switch scale is 4×4, any value of 1 to 4 is applied.

8. 发明专利

JPH10303917A TRAFFIC SHAPING MEANS, ATM EXCHANGE AND ATM-NIC 失效
公开(公告)号：JPH10303917A
公开(公告)日：1998-11-13
申请号：JP11098597
申请日：1997-04-28
申请人： HITACHI LTD
发明人： MAKIMOTO AKIO , OZAKI NAOHIKO , YASUDA TAKESHI , MIYAO MASUAKI , MORIWAKI NORIHIKO , KASAHARA HIROAKI , MATSUOKA MAKOTO
IPC分类号： H04Q3/00 , H04L12/28 , H04L12/815 , H04L12/863
摘要： PROBLEM TO BE SOLVED: To provide a shaping means capable of outputting a free cell and an effective cell at an optional and fixed rate and to effectively construct an ATM(asynchronous transfer mode) exchange capable of accumulating plural interfaces with various kinds of speed (64 kbps×N). SOLUTION: In this shaping means of an ATM cell to output the effective cell and the free cell at a rate of n to m-n, a first storage means 707 to hold a value of n, a second storage means 705 to hold a value of m and a third storage means 706 to hold a variable are provided. When an added value obtained by adding the value held by the first storage means to the value held by the third storage means by an adder 711 is equal to or larger than the value held by the second storage means 705, the effective ATM cell is read from a cell buffer 106 with a selector, the value obtained by subtracting the value held by the second storage means from the added value by a subtractor 709 is simultaneously and newly stored in the third storage means 706 and when the added value is smaller than the value held by the second storage means 705, the free cell is outputted from a free cell pattern holding part 704 and an operation to newly store the added value in the third storage means 705 is simultaneously performed by every cell time.

9. 发明专利

JPH10200541A CELL DIVISION TYPE ATM SWITCH HAVING CELL RESTORATION CHECK FUNCTION 失效
公开(公告)号：JPH10200541A
公开(公告)日：1998-07-31
申请号：JP399597
申请日：1997-01-13
申请人： HITACHI LTD
发明人： MORIWAKI NORIHIKO , MAKIMOTO AKIO , KASAHARA HIROAKI , KANO TETSUO
IPC分类号： H04Q3/00 , H04L12/28
摘要： PROBLEM TO BE SOLVED: To detect whether or not a division origin is the same, before each partial cell is restored into an original cell at a cell combination part of a cell division switch. SOLUTION: In each partial cell switch 2, after a cell multiplex part 12 multiplexes plural partial cells 18 inputted from a cell division part and synchronizes them among the partial cell switches. A time stamp changed in a timing of each multiplexed partial cell time is given to each partial cell by a time stamp giving part 13 and a cell combination part compares time stamps which are given to each partial cell to detect whether or not the division origin is the same.

10. 发明专利

JPH09321766A ATM EXCHANGE 失效
公开(公告)号：JPH09321766A
公开(公告)日：1997-12-12
申请号：JP13222896
申请日：1996-05-27
申请人： HITACHI LTD
发明人： YASUDA TAKESHI , SAKAMOTO KENICHI , KASAHARA HIROAKI , MAKIMOTO AKIO
IPC分类号： H04Q3/00 , H04L12/18 , H04L12/28 , H04L12/70 , H04L12/741 , H04L12/761 , H04L12/931
摘要： PROBLEM TO BE SOLVED: To realize the multi-address function of an ATM exchange by effectively utilizing the hardware of an existent exchange without a multi-address function. SOLUTION: This exchange is provided with a multi-address switch part 61, input line corresponding parts 10 to 1n and output line corresponding parts 20 to 2n to connect each output of not less than two output line corresponding parts 2 to the input of the input lines corresponding parts 1 to constitute a line corresponding part 6 for multi-address processing. A cell sent from an input line to multi-address is given the conversion of a logical channel number and added with an intra-device header by an input header transforming part 3, then sent to plural output line corresponding parts 0 to 2n in a the corresponding part 6 by the switch part 61, given the transformation of a logic channel number by the corresponding parts 0 to In and sent to an output line.

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