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    • 1. 发明专利
    • Selection circuit, and semiconductor device equipped with the same, d/a conversion circuit, and liquid crystal display device
    • 选择电路和配备有其的半导体器件,D / A转换电路和液晶显示器件
    • JP2008033350A
    • 2008-02-14
    • JP2007243846
    • 2007-09-20
    • Fujitsu Ltd富士通株式会社
    • KOKUBU MASATOSHIUTO SHINYA
    • G09G3/36G02F1/133G09G3/20H03M1/74
    • PROBLEM TO BE SOLVED: To provide a selection circuit capable of reducing a transistor appropriation area, a semiconductor device equipped with the same, a D/A conversion circuit, and a liquid crystal display device.
      SOLUTION: There is provided four 2 input selection circuits 50 to 53 for selecting one of two inputs in response with complementary high-order 1 bit selection D2 and *D2 among 3 bit selection signals, and 4 input selection circuits 24A for selecting the inputs in response with complementary low-order 2 bit selection signals D1, *D1, D0, and *D0. In each of the 2 input selection circuits 50 to 53, one end of the two switching transistors is commonly connected and both switching transistors are arranged in the same line and to adjoin each other. The four input selection circuits 24X has four analog switch circuits series connected with the two switching transistors arranged in the same line, is juxtaposed with the analog switch circuits, and is arranged in the same line as the corresponding two input selection circuits. The four input selection circuits may be so constituted as to have the three 2 input selection circuits arranged in a tree form and to select the inputs by a tournament system.
      COPYRIGHT: (C)2008,JPO&INPIT
    • 要解决的问题:提供一种能够减小晶体管占用面积的选择电路,配备该晶体管的区域的半导体器件,D / A转换电路和液晶显示器件。 解决方案:提供四个2个输入选择电路50至53,用于响应于3位选择信号中的互补高阶1位选择D2和* D2选择两个输入中的一个,以及用于选择的4个输入选择电路24A 响应于互补低阶2位选择信号D1,* D1,D0和* D0的输入。 在两个输入选择电路50至53中的每一个中,两个开关晶体管的一端共同连接,并且两个开关晶体管布置在同一条线上并彼此邻接。 四个输入选择电路24X具有与配置在同一直线上的两个开关晶体管连接的四个模拟开关电路,与模拟开关电路并置,并且被布置在与相应的两个输入选择电路相同的直线上。 四个输入选择电路可以被构造成具有以树形布置的三个2输入选择电路并且通过比赛系统选择输入。 版权所有(C)2008,JPO&INPIT
    • 2. 发明专利
    • Operational amplifier, line driver and liquid crystal display device
    • 操作放大器,线路驱动器和液晶显示器件
    • JP2005117547A
    • 2005-04-28
    • JP2003352203
    • 2003-10-10
    • Fujitsu Ltd富士通株式会社
    • KASAI TOSHIHIKOUTO SHINYAKOKUBU MASATOSHIKIZAKI TAKAHIRO
    • G09G3/36G09G3/20H03F3/45
    • H03F3/45753G09G3/3688
    • PROBLEM TO BE SOLVED: To provide an operational amplifier capable of performing offset cancel in a shorter time, and a line driver and a liquid crystal display device capable of shortening one horizontal term. SOLUTION: In the operational amplifier relating to the present invention, a reference voltage during an offset cancel preparation period HC2 is made into an output voltage VO during one preceding horizontal term H1 so that it is enough only to change an output voltage VO(2) just for an offset voltage Voff under feedback control, thereby shortening the required time of feedback control in comparison with a conventional operational amplifier. In the line driver relating to the present invention, the offset cancel operation is performed in the operational amplifier that is not used to output display data D1-D6, and such an operational amplifier is sequentially transited for each horizontal term. Therefore, it is not necessary to include the offset cancel preparation period in an output period, thereby more shortening one horizontal term. COPYRIGHT: (C)2005,JPO&NCIPI
    • 要解决的问题:提供能够在较短时间内执行偏移消除的运算放大器,以及能够缩短一个水平项的线驱动器和液晶显示装置。 解决方案:在本发明的运算放大器中,在偏移消除准备期间HC2期间的参考电压在一个先前的水平项H1期间被形成为输出电压VO,使得仅足以改变输出电压VO (2)仅用于反馈控制下的偏移电压Voff,从而缩短了与传统运算放大器相比所需的反馈控制时间。 在本发明的线路驱动器中,在不用于输出显示数据D1-D6的运算放大器中执行偏移消除操作,并且对于每个水平项,这样的运算放大器顺序地进行。 因此,不需要在输出期间包括偏移抵消准备期间,从而更加缩短一个水平期。 版权所有(C)2005,JPO&NCIPI
    • 4. 发明专利
    • Detection circuit and power supply system
    • 检测电路和电源系统
    • JP2008206226A
    • 2008-09-04
    • JP2007036536
    • 2007-02-16
    • Fujitsu Ltd富士通株式会社
    • KOKUBU MASATOSHIMATSUMOTO TAKASHI
    • H02M3/155H02J1/00H02M7/00
    • H02M3/156H02M3/1588H02M2001/0025Y02B70/1466Y10S323/906
    • PROBLEM TO BE SOLVED: To provide a detection circuit generating a control signal dependent on the power supplied. SOLUTION: Based on a current detection signal S1, a correction current generation circuit 49 generates a correction current Ih proportional to a current supplied from an AC adapter 21. The correction current Ih is supplied to a correction resistor R3. A correction voltage Vh substantially equal to the ground level being offset by the parasitic resistance of a cable W1 is thereby generated at a node between the correction current generation circuit 49 and the correction resistor R3. An operational circuit 48 delivers a correction information voltage Vph generated by adding the correction voltage Vh to a power information voltage Vpw as a power limit signal PWRM to an error amplifier 47. The operational circuit 48 adds the correction voltage Vh to the power information voltage Vpw indicating small power information by offset thus generating a corrected power limit signal PWRM. As a result, a power limit signal PWRM corresponding to the power information outputted from a pulse width modulator 24 is generated. COPYRIGHT: (C)2008,JPO&INPIT
    • 要解决的问题:提供一种根据所提供的功率产生控制信号的检测电路。 解决方案:基于电流检测信号S1,校正电流产生电路49产生与从AC适配器21提供的电流成比例的校正电流Ih。校正电流Ih被提供给校正电阻器R3。 因此,在校正电流产生电路49和校正电阻器R3之间的节点处产生基本上等于由电缆W1的寄生电阻偏移的接地电平的校正电压Vh。 操作电路48将通过将校正电压Vh与作为功率限制信号PWRM的功率信息电压Vpw相加而产生的校正信息电压Vph传递到误差放大器47.运算电路48将校正电压Vh与功率信息电压Vpw 通过偏移指示小功率信息,从而产生校正的功率限制信号PWRM。 结果,产生与从脉宽调制器24输出的功率信息对应的功率限制信号PWRM。 版权所有(C)2008,JPO&INPIT
    • 5. 发明专利
    • Operational amplifier, line driver, and liquid crystal display device
    • 操作放大器,线路驱动器和液晶显示器件
    • JP2007300683A
    • 2007-11-15
    • JP2007207677
    • 2007-08-09
    • Fujitsu Ltd富士通株式会社
    • KASAI TOSHIHIKOUTO SHINYAKOKUBU MASATOSHIKIZAKI TAKAHIRO
    • H03F3/45G09G3/20G09G3/36H03F3/34
    • PROBLEM TO BE SOLVED: To provide an operational amplifier capable of performing offset cancel in a shorter time, and a line driver and a liquid crystal display device capable of shortening one horizontal term.
      SOLUTION: In the operational amplifier relating to the present invention, a reference voltage during an offset cancel preparation period HC2 is made into an output voltage VO during one preceding horizontal term H1 so that it is enough only to change an output voltage VO(2) just for an offset voltage Voff under feedback control, thereby shortening the required time of feedback control in comparison with a conventional operational amplifier. In the line driver, the offset cancel operation is performed in the operational amplifier that is not used to output display data D1-D6, and such an operational amplifier is sequentially transited for each horizontal term. Therefore, it does not need to include the offset cancel preparation period in an output period, thereby more shortening one horizontal term can be achieved.
      COPYRIGHT: (C)2008,JPO&INPIT
    • 要解决的问题:提供能够在较短时间内执行偏移消除的运算放大器,以及能够缩短一个水平项的线驱动器和液晶显示装置。 解决方案:在本发明的运算放大器中,在偏移消除准备期间HC2期间的参考电压在一个先前的水平项H1期间被形成为输出电压VO,使得仅足以改变输出电压VO (2)仅用于反馈控制下的偏移电压Voff,从而缩短了与传统运算放大器相比所需的反馈控制时间。 在线路驱动器中,在不用于输出显示数据D1-D6的运算放大器中执行偏移消除操作,并且对于每个水平项,顺序地转换这样的运算放大器。 因此,不需要在输出期间包括偏移抵消准备期间,从而可以实现更短的一个水平期。 版权所有(C)2008,JPO&INPIT
    • 7. 发明专利
    • Operational amplifier having offset cancel function
    • 具有偏移取消功能的操作放大器
    • JP2003060453A
    • 2003-02-28
    • JP2001247907
    • 2001-08-17
    • Fujitsu Ltd富士通株式会社
    • UTO SHINYAKOKUBU MASATOSHI
    • H03F3/00H03F1/34H03F3/34H03F3/345H03F3/45
    • H03F3/45753
    • PROBLEM TO BE SOLVED: To quicken the response characteristics of an operational amplifier, using offset cancel function.
      SOLUTION: An operational amplifier, which generates an output voltage which is the same as the input voltage at an output terminal (OUT), has a differential circuit (10) for comparing the input voltage with the output voltage to generate output according to the difference thereof, a first and a second output transistors (M7, M11) controlled by the output from the circuit (10) and driving the output terminal (OUT), and a offset cancel circuit (11) connected to the circuit (10) and storing offset amount of the circuit (10). During an offset cancel period, when the offset amount is stored in the circuit (11), the output terminal is driven by the second output transistor (M11), and during an operational amplifier operating period after the offset cancel period, the output terminal is driven by the first output transistor (M7). Since the output terminal is driven by the transistor (M11) in advance during the offset cancel period, the time needed for raising potential to a target value during the operational amplifier operating period is made shorter.
      COPYRIGHT: (C)2003,JPO
    • 要解决的问题:使用偏移消除功能来加快运算放大器的响应特性。 解决方案:产生与输出端(OUT)的输入电压相同的输出电压的运算放大器具有差分电路(10),用于将输入电压与输出电压进行比较,以根据差值产生输出 由电路(10)的输出控制并驱动输出端(OUT)的第一和第二输出晶体管(M7,M11)和连接到电路(10)的偏移消除电路(11) 电路(10)的偏移量。 在偏移消除期间,当偏移量存储在电路(11)中时,输出端子由第二输出晶体管(M11)驱动,并且在偏移消除期间之后的运算放大器运行期间,输出端子 由第一输出晶体管(M7)驱动。 由于输出端子在偏移消除期间预先由晶体管(M11)驱动,所以在运算放大器运行期间将电位上升到目标值所需的时间变短。
    • 8. 发明专利
    • Semiconductor device
    • 半导体器件
    • JP2005072609A
    • 2005-03-17
    • JP2004280500
    • 2004-09-27
    • Fujitsu Ltd富士通株式会社
    • KOKUBU MASATOSHIUTO SHINYA
    • G02F1/1368H01L21/822H01L27/04
    • PROBLEM TO BE SOLVED: To decrease a transistor monopolizing area in a semiconductor device. SOLUTION: N type regions 61-66 are formed in the same column on a P type substrate 60. An interconnect line 67 is a first metal layer interconnect line for connecting between the N type region 65 of one end of one side switching transistor constituting 2 inputs selecting circuit and the N type region 63 of one end of the other side switching transistor constituting selecting circuit. The interconnect lines of gradient potentials V3 and V7 which are supplied to the N type regions 64 and 66 of the same column respectively are formed in the same column of third metal layer and second metal layer, respectively, and adjacently located up and down. COPYRIGHT: (C)2005,JPO&NCIPI
    • 要解决的问题:降低半导体器件中的晶体管垄断区域。 解决方案:在P型衬底60上的同一列中形成N型区域61-66。互连线67是用于连接一侧开关的一端的N型区域65之间的第一金属层布线 构成2输入选择电路的晶体管和构成选择电路的另一侧开关晶体管的一端的N型区域63。 分别提供给同一列的N型区域64和66的梯度电位V3和V7的互连线分别形成在相同的第三金属层和第二金属层的列中,并且上下相邻。 版权所有(C)2005,JPO&NCIPI
    • 9. 发明专利
    • Detection circuit and power supply system
    • 检测电路和电源系统
    • JP2008206225A
    • 2008-09-04
    • JP2007036535
    • 2007-02-16
    • Fujitsu Ltd富士通株式会社
    • KOKUBU MASATOSHIMATSUMOTO TAKASHIITO HIDENOBU
    • H02M3/155
    • H02M3/156G01R19/16542H02M2001/0009
    • PROBLEM TO BE SOLVED: To provide a detection circuit in which the circuit scale can be reduced.
      SOLUTION: A battery detection circuit 34 has a current amplifier 41 to which the voltage at both terminals of a resistor R1 is input, and a current amplifier 42 to which the voltage at both terminals of a resistor R2 is input. The current amplifier 41 outputs a current detection signal S1 by detecting a current Iout flowing through the resistor R1, and the current amplifier 42 outputs a charging current detection signal S2 by detecting a charging current Ichg flowing through the resistor R2. An error amplifier 43 has a first inverted input terminal to which the current detection signal S1 is input and a second inverted input terminal to which the charging current detection signal S2 is input. A current reference signal IOUTM and a reference signal based on a limit current signal IDAC are input to the noninverted input terminal of the error amplifier 43. The error amplifier 43 compares the higher one of the current detection signal S1 and the charging current detection signal S2 with the reference signal and generates an error voltage dependent on the comparison results.
      COPYRIGHT: (C)2008,JPO&INPIT
    • 要解决的问题:提供可以减小电路规模的检测电路。 电池检测电路34具有输入电阻R1的两端的电压的电流放大器41和输入电阻R2两端的电压的电流放大器42。 电流放大器41通过检测流过电阻器R1的电流Iout来输出电流检测信号S1,电流放大器42通过检测流过电阻器R2的充电电流Ichg来输出充电电流检测信号S2。 误差放大器43具有输入电流检测信号S1的第一反相输入端子和输入充电电流检测信号S2的第二反相输入端子。 电流参考信号IOUTM和基于限制电流信号IDAC的参考信号被输入到误差放大器43的非反相输入端。误差放大器43比较电流检测信号S1和充电电流检测信号S2中较高的一个 具有参考信号并根据比较结果产生误差电压。 版权所有(C)2008,JPO&INPIT