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    • 4. 发明专利
    • CABLE DISCONNECTION CHECK SYSTEM
    • JPS6348474A
    • 1988-03-01
    • JP19341986
    • 1986-08-19
    • FUJITSU LTD
    • TANIYAMA YUKIO
    • G01R31/04
    • PURPOSE:To detect a defect in the connection of a connector for cable connection in its early state by checking the cable disconnection of a device connected by the connector for cable connection automatically. CONSTITUTION:Wires corresponding to a 2nd pin P2 and the 50th pin P50 of a PT plate 3 inserted into a PT plate side connector 1 are connected to the connection point of resistors R1 and R2, one terminal side of the resistance R1 is grounded, and one terminal side of the resistor R2 is connected to a power source VCC. Further, those wires are connected to the input terminal of an AND circuit 5 and the voltage states of the 2nd pin P2 and the 50th pin P50 are monitored by an AND circuit 5. In such a state, if the 2nd pin P2 is not connected, an open state is entered and the output of the AND circuit 5 is false. A receiving circuit 4 receiving this state sends out an error signal. When the 2nd pin P2 is connected, a short circuit to the ground is formed, the AND output of the AND circuit 5 becomes true, and the connection OK state of the connector 10 for cable connection is displayed through the receiving circuit 4.
    • 6. 发明专利
    • Additional data writing system of magnetic tape device
    • 磁带设备附加数据写入系统
    • JPS5960715A
    • 1984-04-06
    • JP17149182
    • 1982-09-30
    • Fujitsu Ltd
    • TANIYAMA YUKIOHAYAKAWA AKIHIRO
    • G11B5/09G11B20/12
    • G11B20/12
    • PURPOSE:To avoid reading mistakenly an off-track, i.e., a part of the old data that is unerased by mistake, by starting writing the additional writing data at and after the overwriting end position of a specific pattern with an interblock gap secured. CONSTITUTION:A specific pattern (such as all-1, etc.) is written in an over-write region D, and a standard interblock gap (defined as an IBG' for discrimination from an existing IBG immediately after N block) is formed after the region D. In other words, the IBG' having width equal to the IBG is formed by starting writing (N+1) blocks since a writing head WH is positioned at an area where the tape is erased in its full width when a reading head RH is detecting the rear edge of the region D. Therefore, a region DF including regions B and D can be treated as a defect region where the specific pattern is recorded or the noises remain.
    • 目的:为了避免错误地读取偏离磁道,即旧数据的一部分,这是错误的,这是通过开始在具有固定的间隔间隙的特定图案的覆盖结束位置之后写入附加写入数据。 构成:将特定模式(例如all-1等)写入过写区域D,并且在之后形成标准块间间隙(用于与紧随N块之后的现有IBG区分的IBG') 区域D.换句话说,宽度等于IBG的IBG'通过开始写入(N + 1)块而形成,因为写入头WH位于读取时的磁带被全部擦除的区域 头RH正在检测区域D的后边缘。因此,包括区域B和D的区域DF可以被视为记录特定图案或保留噪声的缺陷区域。
    • 7. 发明专利
    • DATA COMPRESSING CIRCUIT
    • JPS58102314A
    • 1983-06-17
    • JP20213281
    • 1981-12-15
    • FUJITSU LTD
    • TANIYAMA YUKIO
    • H03M7/46G06F3/06G06F5/00G11B20/00G11B20/10
    • PURPOSE:To compress general processed data without any indication regarding the properties of data by software, by representing successive data in succession mode and showing the number of successive data by following data. CONSTITUTION:Data read out of a buffer memory 1 is sent to a gate 11 and also inputted to a register 8 at the same time. A comparing circuit 9 compares the output of the register 8 with the output of the buffer 1. The register 8 holds data which is one byte before and decides on whether the same data succeeds or not. When so, a counter 10 is driven to close the gate 11 and then data which is three bits later is stopped as long as the same data succeeds; once dissident data appears, succeeding data is sent out. Data from the gate 11 is stored in a buffer 4 temporarily. Outputs of write address counters 2 and 5 are supplied to a comparing circuit 6, which compares both to decide on whether the data inputted to the buffer memory 4 is compressed or not.
    • 8. 发明专利
    • ERROR CORRECTING DEVICE
    • JPS57152599A
    • 1982-09-20
    • JP3828181
    • 1981-03-17
    • FUJITSU LTD
    • TANIYAMA YUKIO
    • G06F11/10G06F12/16H03M13/19
    • PURPOSE:To obtain an ECC circuit with LSIs having the same configuration and to reduce the number of pins, by installing plural LSIs having a Hamming code producing matrix with a bit array whose data corresponding section is made to point symmetry, a check bit generating section, and data correcting section. CONSTITUTION:Plural LSIs for error correcting code ECC circuit having a Hamming code producing matrix with a bit array whose data corresponding section MD is central point symmetry, a check code generating section which produces a product which produces module ''2'' of data D0-D7 given from an input terminal and comparison check code C0-C4, and a correcting section which makes corrections on data responding to a half of bit array of the matrix in accordance with the output of the check code generating section and given data, are installed. Then, a check code to be added to the written data is obtained by adding the written data and a comparison check code having all bit contents of 0 (zero) to one LSI 15. Corrections on the whole bits of the data are performed in such a way that the read out data from a memory 16 and a check code to be added to the read out data are added to a pair of LSIs 17, 18 after the centrally symmetrical bit array is converted.
    • 9. 发明专利
    • Diagnosis system
    • 诊断系统
    • JPS54150052A
    • 1979-11-24
    • JP5929478
    • 1978-05-18
    • Fujitsu Ltd
    • TANIYAMA YUKIONAGABORI TETSUOISAKA TETSUOFUJIKI MASAKI
    • G06F11/22G06F3/00G06F11/00G06F13/00
    • PURPOSE: To ensure performance of measurement of the transfer capacity as well as the diagnosis of the error detector circuit by installing the means to vary the timing of the data writing and reading to the data transfer buffer device.
      CONSTITUTION: When the data is transferred, data transfer request signal SVI is sent to channel device 13 from the channel buffer (CB) control circuit. Thus, device 13 sends out the data to CB1 to turn on data transmission signal SVO. The CB control circuit confirms signal SVO and produces the transfer timing signal to transmits it to gate 7 and 10. Thus, signal SVO is turned off. Then device 13 confirms the OFF of SVI and turns off SVO to complete transfer of one data. At the diagnosis time, the timing delay setting value is changed freely to be set to register 15, and thus the transfer timing can be changed freely. As a result, the data transfer timing can be varied between device 13 and CB1 to ensure performance the measurement of the transfer capacity as well as the diagnosis for the adaptability decision of the decision of the decision circuit 6 for detection of the overrun.
      COPYRIGHT: (C)1979,JPO&Japio
    • 目的:通过安装改变数据写入和读取数据传输缓冲器设备的时序的方法,确保对传输容量进行测量以及误差检测器电路的诊断。 构成:当传送数据时,数据传送请求信号SVI从通道缓冲器(CB)控制电路发送到通道装置13。 因此,装置13向CB1发送数据以接通数据发送信号SVO。 CB控制电路确认信号SVO并产生传输定时信号以将其发送到门7和10.因此,信号SVO被关断。 然后设备13确认SVI的关闭,并关闭SVO以完成一个数据的传送。 在诊断时刻,定时延迟设定值自由变化,设定为寄存器15,从而能够自由地变更传送定时。 结果,可以在设备13和CB1之间改变数据传输定时,以确保传输容量的测量性能以及用于判定电路6用于检测超限的决定的适应性决定的诊断。