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1. 发明专利

JPH0746246A LINE CONNECTION NOTICE PROCESSING METHOD AND DEVICE FOR CONSTANT BIT RATE INFORMATION TRANSMISSION IN COMMUNICATION NETWORK IN ASYNCHRONOUS TRANSMISSION MODE 失效
公开(公告)号：JPH0746246A
公开(公告)日：1995-02-14
申请号：JP18836793
申请日：1993-07-29
申请人： NEC CORP , NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD
发明人： KOBAYASHI MASATO , MURAKAMI KOU , UEMATSU HITOSHI , UEDA HIROMI , TAKEO HIROSHI , IGUCHI KAZUO
IPC分类号： H04M3/22 , H04L12/28 , H04L12/70 , H04L12/885 , H04L12/951 , H04M3/42 , H04Q3/00 , H04L12/56
摘要： PURPOSE:To discriminate truly effective CBR information by informing a state to a client side for each transition of a line connection state of a server side. CONSTITUTION:An unsetting state lindicates that a VP of an ATM network is not set and no fault notice is made even on the occurrence of a fault in the ATM network. When the VP is set, the state 1 transits to a read state wait state 2. The state 2 is transited to a fault state 3 when a fault takes place after the transmission of an unsetting line signal in the transient state from the state 1 to the service state 4. When the fault is recovered, the state transits to the state 4. When the fault generates in the server side in the state 4, the communication is interrupted and an alarm notice signal is sent to the client side and the state transits to a fault state 5, and when the fault is recovered, the state transits a read start standby state 6. In the state 6, when data storage in a fluctuation absorbing buffer is finished, the alarm is released and returns to the state 4. It is possible for the client side to discriminate the CMR information received to be effective when the line of the server side is open truly and the state reaches the service available state.

2. 发明专利

JPH06268692A DELAY FLUCTUATION ABSORBING BUFFER MEMORY CONTROL SYSTEM 失效
公开(公告)号：JPH06268692A
公开(公告)日：1994-09-22
申请号：JP23751693
申请日：1993-08-18
申请人： NEC CORP , NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD
发明人： KOBAYASHI MASATO , MURAKAMI KOU , UEMATSU HITOSHI , UEDA HIROMI , TAKEO HIROSHI , IGUCHI KAZUO
IPC分类号： H04L29/14 , H04L12/801 , H04L12/885 , H04L12/911 , H04L12/951 , H04L13/08 , H04Q3/00 , H04L12/48 , H04L12/56
摘要： PURPOSE:To effectively perform recovery processing by performing write or read phase shift or initializing a buffer memory when the overflow or underflow of the buffer memory is generated. CONSTITUTION:When a read address 11 passes ahead a write address 10, a phase difference detection part 12 decides at the underflow of a buffer memory 2 and outputs a decided result 14. When an underflow protection part 15 decides the underflow is more than a certain generation frequency, a read address counter 9 performs processing to delay the read address 11 by the portion of an integer multiple of the frame length of user information. Further, when this processing is performed more than a certain frequency, an initialization protection part 17 generates an initialization control signal 18 and initializes buffer control. When the overflow is generated, the read address counter 9 performs processing to advance the read address 11 by the portion of an integer multiple of the frame length of user information. Further, the processing is performed more than a certain frequency, the buffer control is initialized.

3. 发明专利

JPH06178373A POLISHING CONTROL SYSTEM 失效
公开(公告)号：JPH06178373A
公开(公告)日：1994-06-24
申请号：JP34984392
申请日：1992-12-02
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKEO HIROSHI , KUSAYANAGI MICHIO , YAMANAKA NAOAKI , SATO YOICHI
IPC分类号： H04Q11/04 , H04L12/813 , H04L12/851 , H04L12/48
摘要： PURPOSE:To attain a polishing processing which is flexible in setting an disposal priority order and a collation pattern and to reduce a hardware scale in a polishing control system realizing a UPC function in the subscriber's system of wide band ISDN. CONSTITUTION:This system is provided with plural detection circuits 30 detecting respectively different kinds of cells by being provided parallelly with an input cell current and a logical circuit 31 deciding the kind of an input cell while giving the priority order between the kinds of cells by logical processing the detection signal of the plural detection circuits 30. Then the polishing processing is executed to the input cell based on the deciding result of the logical circuit 31.

4. 发明专利

JPH06177903A POLICING CONTROL SYSTEM 失效
公开(公告)号：JPH06177903A
公开(公告)日：1994-06-24
申请号：JP32392792
申请日：1992-12-03
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKEO HIROSHI , KUSAYANAGI MICHIO , YAMANAKA NAOAKI , SATO YOICHI
IPC分类号： H04L12/48
摘要： PURPOSE:To decrease capacity of a CATM circuit with respect to the policing control system monitoring traffic of cells in an ATM communication system. CONSTITUTION:A system is provided with VPI adaptor sections 6-1 to 6-n (corresponding to each logical path) each comprising a CATM circuit 1, a comparator circuit 2, a VPI filter 3, an X/M-adic counter 4 or the like. Then the VPI filter 3 extracts a discrimination object cell to allow the X/M-adic counter 4 to count up and the CATM circuit 1 writes an arrival time or an arrival interval of cells for each X/M count, that is, for each arrived cell number being 1/M of a specified value X based on a policing application value. The comparator circuit 2 discriminates whether or not the time interval when number of the cells being the specified value X from the CATM circuit 1 exceeds the specified time, and gives violation cell discrimination information when the time interval exceeds the specified time to an abort control section 5, which aborts the arrived cells.

5. 发明专利

JPH0276426A MONITOR AND CONTROL SYSTEM FOR REMOTE STATION 失效
公开(公告)号：JPH0276426A
公开(公告)日：1990-03-15
申请号：JP22950288
申请日：1988-09-13
申请人： FUJITSU LTD
发明人： NAKADE HIROSHI , TAKEO HIROSHI , TAKEDA SATOSHI , YAMAZAKI HIROSHI , MATSUSHIMA HIROMASA
IPC分类号： H04J99/00
摘要： PURPOSE:To allow a monitor and control equipment on the master station side to monitor and control a slave station without dropping the using efficiency of a transmission line by inserting a monitor/control instruction code for the master station side monitor and control equipment into an idle channel to send the code to a slave station equipment. CONSTITUTION:A channel retrieving part 11 in the master station equipment 10 detect idle channels 31s, 32s in reciprocating transmission lines 31, 32 to/from the slave station equipment 20 and connects the channels 31s, 32s to a control part 12. The control part 12 executes silent processing so that monitor/control information sent from the channel 32s is not outputted to the outside of the equipment and drives an instruction inserting part 13. The inserting part 13 inserts an instruction sending code for a control instruction or a monitor instruction from the monitor and control equipment 100 to the equipment 20 into the channel 31s from the master station to the slave station formed as a pair with the channel 32s to send the code to the equipment 20. In the equipment 20, a code detector 21 monitors the signal of a transmitter 31 in each channel and detects the channel 31s into which the instruction sending code from the equipment 100 is inserted to drive the control part 22.

6. 发明专利

JPH0263324A BIT ARRANGEMENT CONVERTING CIRCUIT 失效
公开(公告)号：JPH0263324A
公开(公告)日：1990-03-02
申请号：JP21670888
申请日：1988-08-30
申请人： FUJITSU LTD
发明人： TAKEO HIROSHI , TAKEDA SATOSHI , NAKADE HIROSHI , MIURA NORIHISA , YAMAZAKI HIROSHI
IPC分类号： H03M13/27
摘要： PURPOSE:To realize the function equal to that of a conventional circuit through the use of one register only by connecting parallel output terminals and parallel input terminals and forming an output terminal by required one bit in the parallel output terminals as an output terminal to a transmission line. CONSTITUTION:A parallel output terminal 1c and a parallel input terminal 1b are connected so that an output from the parallel output terminal 1c in a register 1 is inputted to the parallel input terminal 1b according to the bit replacement in a way that the revision rule f(D)-D of the predetermined bit arrangement is not a constant value. Moreover, an output terminal 1c-1 by the required one-bit among the parallel output terminals 1c is formed as the output terminal to the transmission line. Thus, the same function as that of a conventional circuit is realized by having only to use on register and the scale of the hardware is halved.

7. 发明专利

JPH01290331A SYNCHRONIZING PROTECTION SYSTEM 失效
公开(公告)号：JPH01290331A
公开(公告)日：1989-11-22
申请号：JP12086088
申请日：1988-05-18
申请人： FUJITSU LTD
发明人： NAKADE HIROSHI , TAKEO HIROSHI , TAKEDA SATOSHI , YAMAZAKI HIROSHI , MIURA NORIHISA
IPC分类号： H04J3/06 , H04L7/08
摘要： PURPOSE:To reduce the synchronizing recovery time at the reception of a fault generating signal in a host device by adding an output of a fault generating signal detection circuit to a sub synchronizing circuit, bringing the sub synchronizing circuit into out of synchronism state and starting hunting of the sub synchronizing circuit. CONSTITUTION:An output of a fault generating signal detection circuit 500 is fed to a sub synchronizing circuit 300 to bring the sub synchronizing circuit 300 forcibly to out of synchronism state. The sub synchronizing circuit 300 starts instantaneous synchronization retrieval to an output of a synchronizing pattern detection circuit 100 to establish frame synchronization. On the other hand, a master synchronizing circuit 200 uses a fault generating signal to be shifted to out of synchronism state. In this case, when the sub synchronizing circuit 300 is in the synchronizing state, a timing pulse output is fed to the master synchronizing circuit 200, which establishes the synchronizing state. As a result, the synchronizing recovery time at fault restoration is reduced.

8. 发明专利

JPS63226109A PSEUDO RANDOM SIGNAL GENERATING CIRCUIT 失效
公开(公告)号：JPS63226109A
公开(公告)日：1988-09-20
申请号：JP6042187
申请日：1987-03-16
申请人： FUJITSU LTD
发明人： TAKEDA SATOSHI , TAKEO HIROSHI , YAMAZAKI HIROSHI , IKUTA KOJI , HIROSE YUKIO
IPC分类号： H03K3/84
摘要： PURPOSE:To reduce the scale of hardware by starting the processing from a predetermined phase in the entire period of a pseudo random signal periodically among phases whose phase difference from that of a phase control signal is predetermined according thereto. CONSTITUTION:A predetermined value (1) is written in a pseudo random signal generating shift register 1 by receiving a phase control signal given periodically externally, when the value of the shift register reaches a predetermined value (2) while monitoring it, it is detected by a detection circuit 2 to give a timing to write a predetermined value (3) into a shift register. Then the predetermined signals (1), (3) written in the shift register are selected by a selection circuit 3, the selected predetermined signal is written in the shift register, it is detected by an exclusive OR circuit 4, from which a pseudo random signal (4) is generated. Thus, any phase regulating shift register is not required.

9. 发明专利

JPS6261436A NOISE SUPPRESSION SYSTEM 失效
公开(公告)号：JPS6261436A
公开(公告)日：1987-03-18
申请号：JP20201785
申请日：1985-09-12
申请人： FUJITSU LTD
发明人： NAKADE HIROSHI , TAKEDA SATOSHI , OHATA MICHINOBU , TAKEO HIROSHI , YAMAZAKI HIROSHI
IPC分类号： H04J3/12 , H04J3/00
摘要： PURPOSE:To prevent the adverse effect onto other channel due to the oscillation of an unused channel by supervising a signaling data to identify the unused channel and converting the channel not in use into a silent pattern. CONSTITUTION:A signaling supervisory section 14 is a device supervising a dial signal flowing through a channel and a charging signal to supervise the signaling of each channel at an output terminal of a signaling multiplex section 11 and an input terminal of the signaling separation section 12. The result of supervision is sent to a transmission timing generating section 5 and a reception timing generating section. The transmission timing generating section 5 and the reception timing generating section 6 identify the channel not in use based on the result of supervision to be sent, supply no processing to the channel in use but control the voice multiplex section and the voice separation section 8 to send the silent pattern to the channel not in use. The channel not in use is brought into, e.g., all 1 by the control to attain the silence state.

10. 发明专利

JPS6257330A FRAME SYNCHRONIZING PATTERN DETECTING CIRCUIT 失效
公开(公告)号：JPS6257330A
公开(公告)日：1987-03-13
申请号：JP19666885
申请日：1985-09-05
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKEO HIROSHI , OHATA MICHINOBU , TAKEDA SATOSHI , NAKADE HIROSHI , YAMAZAKI HIROSHI , KUNIEDA TOSHINARI , WASHIYAMA IKUO
IPC分类号： H04J3/06 , H04L7/08
摘要： PURPOSE:To attain restoration of synchronization in a short time by a few capacity of shift register function section by discriminating it as the detection of synchronization pattern when the frame synchronizing pattern is detected for a prescribed number of times with plural consecutive bits. CONSTITUTION:Shift register function sections 1-1, 1-2, 1-3, having a fewer number of stages than the rame number in one multi-frame are providing and a specific position of the shift register functions 1-1, 1-2, 1-3, e.g., a head bit is supervised. The frame synchonizing pattern such as S2, S3, S4 exists in the order of the shift register function sections 1-3, 1-2, 1-1, that is, the frame sunchronizing pattern in 3-bit consecution and the frame synchronization pattern is detected in 3-bit consecution even after 193-bit shift, it is checked by a consecutive number of time detection section 3 for th4e detection of prescribed consecutive number of times and it is discriminated as the detection of frame synchronization pattern.

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