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1. 发明专利

JP2002007219A MONITOR SYSTEM 失效
公开(公告)号：JP2002007219A
公开(公告)日：2002-01-11
申请号：JP2000191333
申请日：2000-06-26
申请人： FUJITSU LTD
发明人： FUKUBEYAMA TEIJI , NISHIMURA SATOSHI , FUKUDA TAKASHI , KUBO YUJI , SERIZAWA HIROSHI , NAKADE HIROSHI
IPC分类号： G06F12/16 , G06F3/06 , H04N7/18
摘要： PROBLEM TO BE SOLVED: To provide a monitor system which surely backs up and stores operational information on an object device to be monitored and enables the monitor device and backup memory device, constituting the monitor system to quickly recover from a fault. SOLUTION: The backup memory device is equipped with doubled backup memories which are capable of plane switching, a memory control part which controls the doubled backup memories, and an insertion/extraction flag storage part which detects and stores the insertion/extraction state of the backup memory device, and the monitor device is equipped with a monitor circuit which receives the operational information from a monitored system, a work memory which stores the received operation information, and a plane information storage memory which stores plane information which shows whether the doubled backup memories of the backup memory device are in-use or at a standby.

2. 发明专利

JPH06350679A FAULT DISCRIMINATING METHOD 失效
公开(公告)号：JPH06350679A
公开(公告)日：1994-12-22
申请号：JP13967493
申请日：1993-06-11
申请人： FUJITSU LTD
发明人： HIYAMA SHINJI , NAKADE HIROSHI , TAKEDA SATOSHI , KIMOTO AKIHIKO
IPC分类号： H04L29/14
摘要： PURPOSE:To provide a fault discriminating method for inter-package interface which prevents erroneous discrimination due to the lag generated in the soft processing or the like for package mounting to correctly discriminate a package fault at the time of no response of a control object package to the control from a control package. CONSTITUTION:In each of control object packages 1 to (n), the output of a CRC check circuit 13 of a command/status processing part 10 in a control and monitor system is inputted to the SET side of the input of an F/F 15, and the output of a power-on reset part 18 is inputted to the RESET side of the input of the F/F 15, and the output of the F/F 15 which is reset to the low level till then by the reset signal of the power-on reset part 18 due to power-on is set to the high level by a signal in the low level sent at the time of normal reception of command data from the control package, thereby sending the mounting information of each of control object packages 1 to (n).

3. 发明专利

JPH0622002A IN-EQUIPMENT INFORMATION COLLECTION SYSTEM 失效
公开(公告)号：JPH0622002A
公开(公告)日：1994-01-28
申请号：JP17399992
申请日：1992-07-01
申请人： FUJITSU LTD
发明人： NAKADE HIROSHI , KAMOI NOBUHISA , HIYAMA SHINJI
IPC分类号： H04L29/14 , G06F17/40 , H04Q9/02 , G06F15/74
摘要： PURPOSE:To provide the system facilitating the discrimination of a fault and non-mount when a collected section dose not reply with respect to the system collecting the information of each section in the equipment. CONSTITUTION:When a main collection section 1 issues an instruction of information collection to each collected section 2 and the main collection section 1 collects the information of each collected section 2 by allowing each collected section 2 to reply the instruction, a sub collection section 3 grasping the mount state of each collected section 2 is provided with a specific reply generating means 4 and when the collected section 2 is not mounted on the reception of the information collection instruction to the collected section 2, a specific reply representing non-mount of the collected section 2 is returned to the main collection section 1. When the collected section 2 does not reply with the information collection instruction of the main collection section 1 and the main collection section 1 receives a specific reply, the main collection section 1 discriminates non-mount of the collected section 2 and when no specific reply is received, the section 1 discriminates the collected section 2 to be faulty.

4. 发明专利

JPH04138800A CROSS CONNECTION DEVICE 失效
公开(公告)号：JPH04138800A
公开(公告)日：1992-05-13
申请号：JP26231690
申请日：1990-09-28
申请人： FUJITSU LTD
发明人： MORIMOTO AKIO , NAKADE HIROSHI , OUCHI NOBUAKI
IPC分类号： H04J3/02 , H04J3/00 , H04L12/52 , H04Q11/04
摘要： PURPOSE:To easily obtain a cross connection device consisting of a small--scale hardware by constituting the entirely mounted cross connection device of plural cross connection parts dividing functions between respective input signal line groups and respective output signal line groups in each input signal line group. CONSTITUTION:Respective functions between the input signal line groups 1 to 8 and output signal line groups 1' to 8' of the cross connection device are constituted of the cross connection parts 71 to 78 in each input signal line group and these functions can easily be divided in each cross connection part. In the case of one input signal line group, the cross connection part 71 is used, and in the case of two input signal line groups, the cross connection parts 71, 72 are used. Thereby, the cross connection device of the small-scale hardware can easily be obtained in the case of using eight input signal line groups or less, and produced at a low cost.

5. 发明专利

JPS63262939A FAST SYNCHRONIZATION CIRCUIT 失效
公开(公告)号：JPS63262939A
公开(公告)日：1988-10-31
申请号：JP9773387
申请日：1987-04-20
申请人： FUJITSU LTD
发明人： MIURA NORIHISA , TAKEO HIROSHI , TAKEDA SATOSHI , NAKADE HIROSHI , YAMAZAKI HIROSHI
IPC分类号： H04J3/06 , H04J3/00 , H04L7/08 , H04L13/10 , H04L25/40
摘要： PURPOSE:To secure TSSI(Time Slot Sequence integrity), by providing a cross- connect switch which outputs a parallel signal of (n) bits whose phase is aligned from the input of a parallel signal of (2n-1) bits outputted from a serial-parallel conversion circuit. CONSTITUTION:A frame synchronizing pattern is detected from either plural frame synchronizing pattern detection circuits(300-1-300-n) arranged in parallel is detected, and it is added on the input on one side of a signal switching means 500 as a control signal. Meanwhile, the parallel signal of (2n-1) bits outputted from the serial-parallel conversion circuit 200 is added on the input on the other side of the signal switching means 500. And a switch 5 is switched by the control signal from a frame synchronizing pattern detecting means, and the parallel signal of (n) bits in which a frame synchronizing signal is set at the front and whose phase is aligned is outputted. In such a way, the frame synchronizing signal is set at the front of the parallel output of the cross- connected switch 5, and no mixture of the data of a preceding and a succeeding frames is prevented from occurring, and the TSSI can be secured.

6. 发明专利

JPS6243920A DECODING CIRCUIT 失效
公开(公告)号：JPS6243920A
公开(公告)日：1987-02-25
申请号：JP18359685
申请日：1985-08-21
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKEO HIROSHI , OHATA MICHINOBU , TAKEDA SATOSHI , NAKADE HIROSHI , YAMAZAKI HIROSHI , OKAMOTO KATSUSHIGE , WASHIYAMA IKUO
IPC分类号： H04L25/49 , H03M5/16 , H03M7/46 , H04B14/04
摘要： PURPOSE:To simplify the constitution and to facilitate circuit integration by detecting bipolar violation and using the detection signal to decode a received replacing code. CONSTITUTION:A '0' consecutive code of a prescribed length in a PCM signal is converted into a replacing code by bipolar violation, the replacing code is detected at the reception side and converted into a '0' consecutive code by a decoding circuit. The 1st shift register 1 shifting sequentially the input signal and storing it in the decoder circuit, a violation detection circuit 3 detecting the violation of the input signal, the 2nd shift register 2 inputting the detection signal of the violation detection circuit and a replacing code detection circuit 4 detecting the replacing code inputting the set content of the 1st and 2nd shift registers are provided. Then, the replacing code detection circuit detects the replacing code to control the consecutive '0' for the content of the 1st shift register.

7. 发明专利

JPS6028724A POWER SOURCE BUS SYSTEM 失效
公开(公告)号：JPS6028724A
公开(公告)日：1985-02-13
申请号：JP13827383
申请日：1983-07-28
申请人： FUJITSU LTD
发明人： NAKADE HIROSHI , OGISO MASAAKI , TAKEO HIROSHI , TAKEDA SATOSHI
IPC分类号： H02J1/00

8. 发明专利

JPS6013430A PANEL POWER SOURCE SUPPLY SYSTEM 失效
公开(公告)号：JPS6013430A
公开(公告)日：1985-01-23
申请号：JP11927583
申请日：1983-06-30
申请人： FUJITSU LTD
发明人： TAKEDA SATOSHI , NAKADE HIROSHI , TAKEO HIROSHI , OGISO MASAAKI
IPC分类号： H02J1/00

9. 发明专利

JPH0816538A INTER-PROCESSOR COMMUNICATION SYSTEM 失效
公开(公告)号：JPH0816538A
公开(公告)日：1996-01-19
申请号：JP14782594
申请日：1994-06-29
申请人： FUJITSU LTD
发明人： NISHIMURA SATOSHI , NAKADE HIROSHI
IPC分类号： G06F15/167 , G06F15/163
摘要： PURPOSE:To transfer data between processors at a high speed and to efficiently operate each processor with respect to the inter-processor communication system for the processor system provided with at least two processors. CONSTITUTION:The interrupt data area in a memory 13 which interrupt data is written in and read out consists of plural partitioned interrupt data blocks 25, and processors 11 and 12 on the write side select one or plural continuous processed interrupt data blocks 25 to write the data, and processors 12 and 11 on the read side retrieve and read out one or plural continuous unprocessed interrupt data blocks 25, and each interrupt data block 25 includes the flag area, where a processing flag PF indicating whether interrupt data is already processed or not is written, in a part.

10. 发明专利

JPH05160809A CRC CHECKING METHOD 失效
公开(公告)号：JPH05160809A
公开(公告)日：1993-06-25
申请号：JP31827291
申请日：1991-12-03
申请人： FUJITSU LTD
发明人： HAYASHI TOSHIAKI , NAKADE HIROSHI , HIYAMA SHINJI , TAKEDA SATOSHI , OBA MASASHI
IPC分类号： G06F11/10 , H03M13/09 , H04L1/00
摘要： PURPOSE:To obtain a CRC checking method with a small circuit scale and a low cost. CONSTITUTION:A CRC arithmetic operation is implemented by 'N-1' frames based on the result of CRC arithmetic operation of data of each CH in a preceding frame and on the data of the same CH in a succeeding frame at a CRC arithmetic operation means 2 of a transmission side path to obtain a CRC code to be added and the code is written in a CRC code area of the relevant CH of the N-th frame and sent to a cross connect device 1. The CRC arithmetic operation is implemented by 'N' frames based on the half-way result of CRC arithmetic operation of the data of each CH in a received frame and on the data of the same CH in a preceding frame at a CRC arithmetic operation means 3 of a reception side path to obtain the CRC arithmetic operation. A comparison write means 4 reads the CRC arithmetic operation results up to a preceding period from the memory 5, compares the results and writes the result of comparison to the memory 5 so that the result of comparison discordance is left by M periods only when the results are discordant.

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