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1. 发明专利

JPS6156424A Mounting method for chip carrier 失效
标题翻译：芯片载体的安装方法
公开(公告)号：JPS6156424A
公开(公告)日：1986-03-22
申请号：JP17861984
申请日：1984-08-28
申请人： Fujitsu Ltd
发明人： INAGAKI MITSUO , MURASE HIROSHI , TSUBONE KENICHIRO
IPC分类号： H05K1/18 , H01L21/60 , H05K3/34
CPC分类号： H01L24/81 , H01L2224/81801 , H01L2924/014 , H05K3/3431
摘要： PURPOSE:To enhance the reliability of soldering by reducing the repeated shearing stress applied to solder layers, and then eliminating crack generation in solder layers, by a method wherein the chip carrier is soldered at the center of its back. CONSTITUTION:The side wall of the chip carrier 2 made of a ceramic base is provided with terminals 8 connected to electrode patterns 7, and the back is provided with the second electrode patterns 30 at the center which are connected to the first electrode pads 29 with conductor patterns 30a. The first and second substrate pads 20 and 21 are connected to the surface of a hybrid IC substrate 1 made of ceramic 1 with conductor patterns 21a. The substrate pads are soldered to the electrode pads with solder layers 22 and 23. The difference in the amount of thermal expansion between the carrier 2 and the substrate 1 at the part of the second solder layer 23 is made much smaller than the part of the first solder layer 22, and the repeated shearing stress applied to the second solder layer 23 is small.
摘要翻译：目的：通过减少施加到焊料层的重复剪切应力，然后通过其芯片载体焊接在其背面的中心的方法来提高焊接的可靠性，然后消除焊料层中的裂纹产生。构成：由陶瓷基座制成的芯片载体2的侧壁设置有连接到电极图案7的端子8，并且背面在中心设置有与第一电极焊盘29连接的第二电极图案30，导体图案30a。第一和第二基板焊盘20和21连接到具有导体图案21a的由陶瓷1制成的混合IC基板1的表面。衬底焊盘用焊料层22和23焊接到电极焊盘。在第二焊料层23的部分处，载体2和衬底1之间的热膨胀量的差异远远小于第一焊料层22和施加到第二焊料层23的重复剪切应力小。

2. 发明专利

JPS60177665A MANUFACTURE OF DIP-TYPE ELECTRONIC PARTS 失效
公开(公告)号：JPS60177665A
公开(公告)日：1985-09-11
申请号：JP3323584
申请日：1984-02-23
申请人： FUJITSU LTD
发明人： KUMAI TOSHIO , KOBAYASHI SHIGEKATSU , MURASE HIROSHI
IPC分类号： H05K1/18 , H01L23/28 , H01L23/495 , H01L23/50 , H05K3/30
摘要： PURPOSE:To massproduce DIP-type electronic parts with low cost, by packaging them with a fluid fine-particle soaking method. CONSTITUTION:Terminals of a ceramic substrate 4 on which there is an electronic circuit with electronic parts mounted thereon are held between tips of terminals 6 with a comb shape formed integrally with a lead frame 6A having a belt shape and tips of terminals 7 with a comb shape formed integrally with another lead frame and bended in advance by 180 deg.. They are coated with soldering paste and soldered as well as the electronic parts on the substrate 4, to arrange in parallel multiple electronic bodies 8 between two lines of the lead frames. When the bodies 8 are heated above the melting temperature of fine- particle resin 22 and are soaked in a fluid bath 20 with the lead frames held, the melting fine particle resin 22 adheres to the surface of the bodies 8 to form package 9. After the lead frames are cut off, each terminal 6 is bended in L- shape while each terminal 7 is inserted into a socket 11 of a lead terminal assembly 10 with sockets respectively. In this way, DIP-type parts which have the terminals 6 and L-shape terminals 12 being arranged in parallel on one side of the package 6 are finished.

3. 发明专利

JPS5897893A METHOD OF MOUNTING CHIP PART ON PRINTED BOARD 失效
公开(公告)号：JPS5897893A
公开(公告)日：1983-06-10
申请号：JP19622781
申请日：1981-12-08
申请人： FUJITSU LTD
发明人： OONISHI HIROSHI , MURASE HIROSHI , ABE TOSHIO
IPC分类号： H05K3/34

4. 发明专利

JPS5877290A METHOD OF FIXING CHIP PART 失效
公开(公告)号：JPS5877290A
公开(公告)日：1983-05-10
申请号：JP17592781
申请日：1981-11-02
申请人： FUJITSU LTD
发明人： OONISHI HIROSHI , MURASE HIROSHI , TERASAKI HIROSHI
IPC分类号： H05K3/34

5. 发明专利

JPS57107098A PRINTED BOARD UNIT COOLING SYSTEM 失效
公开(公告)号：JPS57107098A
公开(公告)日：1982-07-03
申请号：JP18471480
申请日：1980-12-25
申请人： FUJITSU LTD
发明人： OONISHI HIROSHI , ABE TOSHIO , MURASE HIROSHI
IPC分类号： H05K7/20

6. 发明专利

JPS5617098A METHOD OF PRINTING PATTERN FOR PRINTED BOARD 失效
公开(公告)号：JPS5617098A
公开(公告)日：1981-02-18
申请号：JP9159879
申请日：1979-07-20
申请人： FUJITSU LTD
发明人： MURASE HIROSHI , TSUCHIYA AKIRA
IPC分类号： H05K3/00

7. 发明专利

JPS5158672A DENKIKETSUSENTAINO SEIZOHOHO 失效
公开(公告)号：JPS5158672A
公开(公告)日：1976-05-22
申请号：JP13340674
申请日：1974-11-20
申请人： FUJITSU LTD
发明人： KOIKE JUNICHI , TSUJI KAZUHIRO , SUNADA TSUNEMI , MURASE HIROSHI , WAKABAYASHI YASUNORI
IPC分类号： H05K3/10 , H05K3/00

8. 发明专利

JPS63227097A METHOD OF THICK FILM THROUGH-HOLE LAND 失效
公开(公告)号：JPS63227097A
公开(公告)日：1988-09-21
申请号：JP6182987
申请日：1987-03-17
申请人： FUJITSU LTD
发明人： MURASE HIROSHI , NODA AKIO
IPC分类号： H05K3/40 , H05K3/12 , H05K3/46

9. 发明专利

JPS62136061A LEAD TERMINAL ATTACHING METHOD FOR HYBRID INTEGRATED CIRCUIT MODULE 失效
公开(公告)号：JPS62136061A
公开(公告)日：1987-06-19
申请号：JP27758185
申请日：1985-12-09
申请人： FUJITSU LTD
发明人： MURASE HIROSHI , HIROSE ATSUKO
IPC分类号： H01L23/50 , B23K1/08 , H01L21/48 , H05K3/34 , H05K3/40
摘要： PURPOSE:To protect a mounted parts from falling-off and the generation of solder bridging by a method wherein lead terminals are attached to a hybrid integrated circuit module and a melted solder surface is vibrated while the upper surfaces of the lead terminals are on the same level as the melted solder surface. CONSTITUTION:A plurality of lead terminals 2 are attached to pads 3 formed on a hybrid integrated circuit module 1 made of ceramic or the like. The lead terminals 2 are dipped in melted solder 5 so as to make the melted solder 5 surface and the upper surfaces of the lead terminals 2 on the same level and the hybrid integrated circuit module is vibrated several times as shown by the arrow mark with an amplitude twice the depth of the surface tension of that condition. With this constitution, the upper surfaces of the lead terminals 2 are intermittently wetted and can be bonded easily and, even if a mounted part 6 which is mounted close to the lead terminal 2 descends to the height of the melted solder 5 surface, it is not wetted because it is positioned inside the recessed part formed by a surface tension so that falling-off and solder bridging can be avoided.

10. 发明专利

JPS61199642A ARMORING METHOD FOR HYBRID INTEGRATED CIRCUIT 失效
公开(公告)号：JPS61199642A
公开(公告)日：1986-09-04
申请号：JP4166485
申请日：1985-03-01
申请人： FUJITSU LTD
发明人： TAKABAYASHI HIROYUKI , MURASE HIROSHI , TSUBONE KENICHIRO
IPC分类号： H01L21/56 , H05K3/28
摘要： PURPOSE:To enable to perform the armoring of a hybrid integrated circuit easily and completely by a method, before parts are mounted on the part- mounting surface of the substrate of the hybrid integrated circuit, the mounting parts are mounted after a picture-frame shaped dam is formed and hardened on the circumference of the substrate, and synthetic resin is poured into said dam. CONSTITUTION:The prescribed pattern 2 is formed on a DIP type circuit substrate 1, and a picture-frame shaped dam 5, consisting of synthetic resin such as polyimide and the like, for example, is molded and hardened along the circumference of the part-mounting surface of the circuit substrate 1 under the condition wherein a number of lead terminals 4 are provided. Then, after the prescribed mounting part 5 is mounted on the substrate 1, liquid synthetic resin such as polyimide and the like is poured into the formed and hardened dam 5, and a resin coating is formed by natural-hardening the liquid synthetic resin to the degree that is does not flow out from the dam 5.

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