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1. 发明专利

JPS61139093A Ceramic multilayer printed wiring board 失效
标题翻译：陶瓷多层印刷接线板
公开(公告)号：JPS61139093A
公开(公告)日：1986-06-26
申请号：JP26055384
申请日：1984-12-10
申请人： Fujitsu Ltd
发明人： HIROSE ATSUKO , MURAKAMI MICHIAKI
IPC分类号： H05K3/46

2. 发明专利

JPS63126668A SOLDER PASTE COATING DEVICE 失效
公开(公告)号：JPS63126668A
公开(公告)日：1988-05-30
申请号：JP27208986
申请日：1986-11-14
申请人： FUJITSU LTD
发明人： TSUBONE KENICHIRO , HIROSE ATSUKO , SUZUKI YUKO
IPC分类号： B23K3/06 , H05K3/34
摘要： PURPOSE:To coat the optimum amt. of solder on a refining connection land by using the nozzle provided with the recessed part in the specified shape at the tip, injecting instantaneously a gas from the inner part by filling a solder paste in the recessed part and sticking the solder to a connection land. CONSTITUTION:In case of coating a solder paste 1 on the connection land 21 of a printed circuit board 2, the nozzle 3 having at the tip the recessed part 4 that a coating area and amt. are decided according to the shape and provided with the gas passage 31 passing to the tip from the inner side is prepared. A solder paste 1 is filled up to the recessed part 4 at the tip of this nozzle 3, which is moved onto a connection land 21, a gas is instantaneously injected from the inside of the nozzle 3 and the solder paste 1 of the recessed part 4 is sprayed and coated on the connection land 21. The optimum amt. of the solder paste 1 is thus coated correctly in the specified shape on the refined connection land 21.

3. 发明专利

JPS62262495A HYBRID INTEGRATED CIRCUIT 失效
公开(公告)号：JPS62262495A
公开(公告)日：1987-11-14
申请号：JP10610886
申请日：1986-05-09
申请人： FUJITSU LTD
发明人： KUTOKU TERUYOSHI , HIROSE ATSUKO
IPC分类号： H05K3/46

4. 发明专利

JPS63204793A CONSTRUCTION OF INTERCONNECTION OF CIRCUIT BOARD 失效
公开(公告)号：JPS63204793A
公开(公告)日：1988-08-24
申请号：JP3893687
申请日：1987-02-20
申请人： FUJITSU LTD
发明人： SUZUKI YUKO , TSUBONE KENICHIRO , HIROSE ATSUKO
IPC分类号： H05K3/46 , H05K1/11

5. 发明专利

JPS62136061A LEAD TERMINAL ATTACHING METHOD FOR HYBRID INTEGRATED CIRCUIT MODULE 失效
公开(公告)号：JPS62136061A
公开(公告)日：1987-06-19
申请号：JP27758185
申请日：1985-12-09
申请人： FUJITSU LTD
发明人： MURASE HIROSHI , HIROSE ATSUKO
IPC分类号： H01L23/50 , B23K1/08 , H01L21/48 , H05K3/34 , H05K3/40
摘要： PURPOSE:To protect a mounted parts from falling-off and the generation of solder bridging by a method wherein lead terminals are attached to a hybrid integrated circuit module and a melted solder surface is vibrated while the upper surfaces of the lead terminals are on the same level as the melted solder surface. CONSTITUTION:A plurality of lead terminals 2 are attached to pads 3 formed on a hybrid integrated circuit module 1 made of ceramic or the like. The lead terminals 2 are dipped in melted solder 5 so as to make the melted solder 5 surface and the upper surfaces of the lead terminals 2 on the same level and the hybrid integrated circuit module is vibrated several times as shown by the arrow mark with an amplitude twice the depth of the surface tension of that condition. With this constitution, the upper surfaces of the lead terminals 2 are intermittently wetted and can be bonded easily and, even if a mounted part 6 which is mounted close to the lead terminal 2 descends to the height of the melted solder 5 surface, it is not wetted because it is positioned inside the recessed part formed by a surface tension so that falling-off and solder bridging can be avoided.

6. 发明专利

JPS6263486A LAMINATED STRUCTURE FOR HYBRID INTEGRATED CIRCUIT 失效
公开(公告)号：JPS6263486A
公开(公告)日：1987-03-20
申请号：JP20283985
申请日：1985-09-13
申请人： FUJITSU LTD
发明人： KUTOKU TERUYOSHI , OMORI SHIGERU , HIROSE ATSUKO
IPC分类号： H05K1/14 , H05K7/14

7. 发明专利

JPS63139402A CHIP TYPE DELAY ELEMENT 失效
公开(公告)号：JPS63139402A
公开(公告)日：1988-06-11
申请号：JP28804086
申请日：1986-12-02
申请人： FUJITSU LTD
发明人： HIROSE ATSUKO , SUGIKI HIROYASU , TSUBONE KENICHIRO , SUZUKI YUKO
IPC分类号： H01P9/00 , H03H7/30
摘要： PURPOSE:To be low in an actually loading height, small and to facilitate a delaying time adjustment by making a conducting chip substrate into an earth electrode, forming a desired snacked delaying line pattern on a insulating layer formed at a conductive chip substrate and providing further a pat at both terminals of a delay line pattern and a bending part. CONSTITUTION:On the whole surface of the surface of a conductive chip substrate 11, an insulating layer 12 composed of the oxide film formed, and a snaked delay line pattern 13 having a desired long line length is formed on the insulating layer 12. A terminal pat 14 is formed at both terminals of the delay line pattern 133 so that a chip type delay element can be serially connected through a terminal line 16 to a signal line 22 of a circuit substrate 20. Further, an intermediate pat 15 is formed at respective bending parts of the delay line pattern 13, and through a short-circuit line 17, the mutual section of a selected intermediate pat 15 or the selected intermediate pat 15 and the terminal pat 14 are short-circuited. Consequently, the conductive chip substrate 11 can be miniaturized. After actually loading onto the circuit substrate 20, through the short-circuit line 17, the mutual section between the selected intermediate pat 15 or the selected intermediate pat 15 and the terminal pat 14 are short- circuited, and the delaying time can be easily adjusted.

8. 发明专利

JPS63107193A METHOD OF FORMING THICK FILM THROUGH-HOLE 失效
公开(公告)号：JPS63107193A
公开(公告)日：1988-05-12
申请号：JP25396686
申请日：1986-10-24
申请人： FUJITSU LTD
发明人： SUZUKI YUKO , TSUBONE KENICHIRO , HIROSE ATSUKO
IPC分类号： H05K3/40

9. 发明专利

JPS61218079A TERMINAL CONNECTOR FOR MOUNTING TWO SIDES 失效
公开(公告)号：JPS61218079A
公开(公告)日：1986-09-27
申请号：JP5850285
申请日：1985-03-25
申请人： FUJITSU LTD
发明人： TANIGUCHI MASAHITO , HIROSE ATSUKO

10. 发明专利

JPS63119290A MANUFACTURE OF THROUGH-HOLE 失效
公开(公告)号：JPS63119290A
公开(公告)日：1988-05-23
申请号：JP26518686
申请日：1986-11-06
申请人： FUJITSU LTD
发明人： TSUBONE KENICHIRO , SUGIKI HIROYASU , HIROSE ATSUKO , SUZUKI YUKO
IPC分类号： H05K3/40

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