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1. 发明专利

JPS60181956A INTERFACE CONTROLLING SYSTEM 失效
公开(公告)号：JPS60181956A
公开(公告)日：1985-09-17
申请号：JP3787384
申请日：1984-02-29
申请人： FUJITSU LTD
发明人： MORIYOSHI SHIYUUHEI
IPC分类号： G06F13/14 , G06F13/26
摘要： PURPOSE:To process preferentially an interruption from a lower rank device by reporting a busy status to a start signal sent from other high rank device until a response is received from a high rank device designated by the interruption concerned. CONSTITUTION:When interrupting information is outputted to a higher rank device 11 from a lower rank device 31, a reception obstructing state is formed against a start signal from other higher rank devices 12, 13 than the higher rank devices concerned. At the same time, an interrupting signal is outputted to the higher rank device 11 concerned for a prescribed time, and in case when a response signal is not received within the prescribed time concerned, said obstructing state is released. Thereafter, a busy status is reported to the optional higher rank device 12 or 13 which has outputted the start signal, and on the other hand, the interruption signal is outputted again for a prescribed time to the higher rank device concerned 11. Accordingly, the interruption from the lower rank device can be executed preferentially against the start from the higher rank device.

2. 发明专利

JPS60214052A Error reporting system 失效
标题翻译：错误报告系统
公开(公告)号：JPS60214052A
公开(公告)日：1985-10-26
申请号：JP7036884
申请日：1984-04-09
申请人： Fujitsu Ltd
发明人： MORIYOSHI SHIYUUHEI
IPC分类号： G06F9/22 , G06F11/00 , G06F11/07 , G06F11/30
CPC分类号： G06F11/0745 , G06F11/0703
摘要： PURPOSE:To report an important trouble speedily and properly by reporting an important error of a microprocessor itself to a host device even in case of its occurrence and recovering the microprocessor with a recovery indication from the host device. CONSTITUTION:When an MPU5 is in operation under microprogram control, a a microprogram detects an important error relating to logical contradiction in a microprogram and then executes a microprogram stop instruction in the microprogram. When the microprogram stop instruction is executed, the microprogram interrupts the operation and the MPU5 outputs an error stop signal to an OR circuit 7 at the same time; and the signal is ORed with the output of an error detecting circuit 4 and the result is outputted to an error reporting circuit 6. The error signal is transmitted to the host device 1 and an instruction indication of selective resetting is sent to a controller 2.
摘要翻译：目的：通过向主机设备报告微处理器本身的重要错误，即使发生故障并通过主机设备恢复指示恢复微处理器，即可快速正确地报告重要故障。构成：当MPU5在微程序控制下运行时，微程序检测与微程序逻辑矛盾有关的重要错误，然后在微程序中执行微程序停止指令。当执行微程序停止指令时，微程序中断操作，MPU5同时向OR电路7输出错误停止信号; 并且该信号与错误检测电路4的输出进行“或”运算，并将结果输出到错误报告电路6.该错误信号被发送到主机1，而选择性复位的指令指示被发送到控制器2。

3. 发明专利

JPS60211535A Control method of magnetic tape 失效
标题翻译：磁带控制方法
公开(公告)号：JPS60211535A
公开(公告)日：1985-10-23
申请号：JP6887684
申请日：1984-04-06
申请人： Fujitsu Ltd
发明人： MORIYOSHI SHIYUUHEI
IPC分类号： G06F3/06 , G06F12/00
摘要： PURPOSE: To prevent waiting time of a controller and to improve the processing efficiency by allowing a controller to receive a detection signal of an index signal from a magnetic device to bring the mode to the data transfer mode with the magnetic tape device.
CONSTITUTION: In a data recording mechanism (DRD)26, an index information detecting section 48 to detect index information added to the head of a unit data is provided and when the index information is detected, it is used as a positioning end signal and transmitted by a primary controller (DIR)20 via a DRD interface circuit 38. After a positioning signal detecting section 36 detects the said positioning end signal, the DIR20 is brought into the data transfer wait state. If no data transfer request signal is transmitted from an interface 38 within a prescribed time, the data transfer waiting state of the DIR20 is released and the other processing, e.g., the intermitted control of access control ARC18 is executed.
COPYRIGHT: (C)1985,JPO&Japio
摘要翻译：目的：为了防止控制器的等待时间，并且通过允许控制器从磁性装置接收到索引信号的检测信号来提高处理效率，以使该模式与磁带装置进行数据传输模式。构成：在数据记录机构（DRD）26中，设置检索附加到单位数据的头部的索引信息的索引信息检测部48，并且当检索到索引信息时，将其用作定位终端信号并发送通过DRD接口电路38通过主控制器（DIR）20。在定位信号检测部分36检测到所述定位终端信号之后，DIR20进入数据传输等待状态。如果在规定时间内没有从接口38发送数据传送请求信号，则DIR20的数据传送等待状态被解除，并且执行其他处理，例如进入控制ARC18的中断控制。

4. 发明专利

JPS582947A WAITING TIME CONTROLLING SYSTEM 失效
公开(公告)号：JPS582947A
公开(公告)日：1983-01-08
申请号：JP10113281
申请日：1981-06-29
申请人： FUJITSU LTD
发明人： MORIYOSHI SHIYUUHEI , TANIYAMA YUKIO
IPC分类号： G06F9/22 , G06F11/28
摘要： PURPOSE:To set a waiting time optionally by an operand value, by subtracting the value of a counter by the value of the operand of a specific instruction when the specific instruction is detected by a decoding circuit and executing the next program when the value of the counter becomes zero. CONSTITUTION:A program fetched from a control storage 2 where microprograms are stored is set to a program register 3; and when an instruction decoding circuit 4 detects a specific instruction in the program from the register 3, the operand part of this instruction is set to a counter 5 through an AND gate. An FF indicating that this specific instruction is executed is set. When the FF is set, an address register 1 for the access to the next instruction is not updated, and a subtracting circuit 7 is operated to count down the counter 5. When the value of the counter 5 becomes zero, the FF is reset, and an address updating circuit 8 is operated, and the register 1 is updated to the address of the next instruction, and the next instruction is fetched.

5. 发明专利

JPS57111743A MICROPROGRAM CONTROLLING SYSTEM 失效
公开(公告)号：JPS57111743A
公开(公告)日：1982-07-12
申请号：JP18761880
申请日：1980-12-29
申请人： FUJITSU LTD
发明人： MORIYOSHI SHIYUUHEI , TANIYAMA YUKIO
IPC分类号： G06F9/22 , G06F9/26
摘要： PURPOSE:To decrease the number of microprograms, by setting and resetting a status register by a hardware circuit when a corresponding branch condition has been formed, in a state that the status register is in a prescribed status. CONSTITUTION:A micro instruction from a control memory CS2 is set to a program output register 1, and an address for reading out the instruction from CS2 is set to an instruction address register 3. A data set to a condition branch section CH of the register 1 is decoded by a decoder 4, and its output controls a status register ST2 through an NAND circuit 5. ST0-ST3 are set and reset by a signal transferred from an operation part ALU, a state of STs 0, 2 is detected by a multiplexer MX6, and a state of STs 1, 3 is detected by an MX7. The MXs 6, 7 select a state of ST0-ST3 in accordance with branch condition sections CH, CL of the register 1, respectively, sets it to the register 3, and when the branch condition has been formed, ST2 is reset automatically.

6. 发明专利

JPS5729125A Data transfer system 失效
标题翻译：数据传输系统
公开(公告)号：JPS5729125A
公开(公告)日：1982-02-17
申请号：JP10388080
申请日：1980-07-29
申请人： Fujitsu Ltd
发明人： MORIYOSHI SHIYUUHEI , TAKIZAWA HIROYUKI
IPC分类号： G06F13/42
CPC分类号： G06F13/4226
摘要： PURPOSE:To prevent the influence of the deformation of a waveform on a transmission by receiving a data transmitted signal which indicates the transmission of data, and then by generating a data set pulse DSP by differentiating the leading and trailing edges of the received signal. CONSTITUTION:For data transfer from an input and output equipment 1' to an input and output controller 2', transfer data is set in a data buffer 10. The equipment 1' generates a data transmitted signal, which indicates the transmission of data from a control circuit 12, a prescribed security time later, and the signal is sent to the controller 2' via an AND gate 14 and a driver 15. The controller 2' receives the signal by a receiver 18 and a differentiating circuit 19 differentiates the leading and trailing edges of the signal to generate a DSP through an AND gate 21, thereby setting the data from a receiver 16 by applying the signal to a data buffer 17. Since the data is sent in the buffer by two DSPs in each cycle of the data received signal, the influence of a waveform deformed on the transmission line is prevented. After the data transfer, counters 13 and 20 generate outputs 1 to suppress the DSPs.
摘要翻译：目的：通过接收指示数据传输的数据发送信号，然后通过区分接收信号的前沿和后沿来产生数据组脉冲DSP来防止波形变形对传输的影响。构成：对于从输入和输出设备1'到输入和输出控制器2'的数据传输，传输数据被设置在数据缓冲器10中。设备1'产生数据传输信号，其指示从控制电路12，稍后规定的安全时间，并且信号经由与门14和驱动器15发送到控制器2'。控制器2'由接收器18和差分电路19接收信号，以区分前导和信号的后沿以通过与门21产生DSP，从而通过将信号施加到数据缓冲器17来设置来自接收器16的数据。由于数据在数据的每个周期中由两个DSP在缓冲器中发送接收信号，防止了在传输线上变形的波形的影响。在数据传输之后，计数器13和20产生输出1以抑制DSP。

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