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1. 发明专利

JPS62206959A MULTIPLEX ANNOUNCEMENT EQUIPMENT 失效
公开(公告)号：JPS62206959A
公开(公告)日：1987-09-11
申请号：JP4901286
申请日：1986-03-06
申请人： FUJITSU LTD
发明人： KITAMURA NOBUAKI
IPC分类号： H04M3/50
摘要： PURPOSE:To listen to an announcement message from the beginning by providing a voice memory storing plural announcement messages to each address and a multiplex address control circuit transmitting an announcement address for transmitting the required announcement message to a voice memory. CONSTITUTION:When a subscriber 8 gives a call, a central controller 10 connects the subscriber 8 via an exchange switch 9 to one of multiplex channels of a signal highway 4 to a send a high-order announcement address representing the announcement message kind to a multiplex address control circuit 2. The control circuit 2 uses a reset circuit to reset a low-order announcement address representing voice sample data to be set at the point of time to the start address and sends the result to a voice memory 1. The voice memory 1 uses the announcement address to send a required announcement message. The control circuit 2 steps the start address of the low-order announcement address to send a new address to the voice memory 1 one after another to transmit the announcement message to the subscriber 8 continuously.

2. 发明专利

JPS6170892A Subscriber circuit 失效
标题翻译：订户电路
公开(公告)号：JPS6170892A
公开(公告)日：1986-04-11
申请号：JP19222284
申请日：1984-09-13
申请人： Fujitsu Ltd
发明人： KITAMURA NOBUAKI
IPC分类号： H04Q3/42 , H04M3/00
CPC分类号： H04M3/005
摘要： PURPOSE:To decrease a load of a central processing type device by installing a monitoring control function to a subscriber circuit. CONSTITUTION:A subscriber circuit 1' has a subscriber interface part 11, a signal processing processor 14 equipped with a PB signal receiving circuit, etc., a program showing a signal processing procedure of the processor 14, a program memory 15 storing subscriber information needed for signal processing and a control circuit 16 transmitting and receiving respective kinds of control signals (b), a sound signal (c), etc. The processor 14 monitors an outgoing call and an incoming call based upon monitoring information transferred from the circuit 16. The circuit 16 identifies a rewriting control signal of the control signals (b) and inputs renewed data included in the rewriting control signal to the memory 15.
摘要翻译：目的：通过向用户电路安装监控控制功能，减少中央处理型设备的负载。构成：用户电路1'具有用户接口部分11，配备有PB信号接收电路的信号处理处理器等，显示处理器14的信号处理过程的程序，存储所需的用户信息的程序存储器15 用于信号处理的控制电路16和发送和接收各种控制信号（b），声音信号（c）等的控制电路16.处理器14基于从电路16传送的监视信息来监视呼出呼叫和来电。电路16识别控制信号（b）的重写控制信号，并将包含在重写控制信号中的更新数据输入到存储器15。

3. 发明专利

JPS6010819A ADAPTIVE TYPE ECHO CANCELLOR 失效
公开(公告)号：JPS6010819A
公开(公告)日：1985-01-21
申请号：JP11695683
申请日：1983-06-30
申请人： FUJITSU LTD
发明人： KITAMURA NOBUAKI , USAMI TAKASHI
IPC分类号： H04B3/23
摘要： PURPOSE:To relax as required a requested internal processing speed by providing a prescribed delay to an estimate operation of an echo line response at next time from the response of estimate echo line at a time by means of the study identification method so as to apply adaptive correcting processing. CONSTITUTION:An input signal is coded by an A/D converter 41 and stored in a register 42 as an input signal time series (xj). A prescribed operation is applied to an output x'j of the register 42 at a time jT ((j) is an integral number and T is a sample period) and an estimate echo response h'j from an echo response (h) register 43 at a convolution circuit 45, an estimated echo signal by D/A-converting 49 the output and the difference between said signal and an actual echo signal Y is operated by a subtractor 50. A specific formula is operated by operating circuits 44, 47 and a correction circuit 46 from a signal as result of A/D conversion 48 of a residual difference output of the subtractor 50 and a signal giving delays 51, 52 to the signal x'j so as to obtain an estimate echo line response h'j+1 at the next time (j+1)T.

4. 发明专利

JPS59229958A MULTIFRAME SYNCHRONOUS TEST SYSTEM 失效
公开(公告)号：JPS59229958A
公开(公告)日：1984-12-24
申请号：JP10413183
申请日：1983-06-13
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： MORI MAKOTO , IWASE YASUMASA , SHIRAISHI YOSHIKATSU , SHIRASAWA SUSUMU , KITAMURA NOBUAKI
IPC分类号： H04J3/14 , H04M3/24 , H04M3/26 , H04Q11/04
摘要： PURPOSE:To classify and assign a trouble occurring to a time-division exchange, to eliminate the need for a communication between controllers, and to simplify a test by facilitating an autonomous test of multiframe synchronism in a digital signal device. CONSTITUTION:When a selection signal (a) is applied to a selection part 106 while a signal (d) is sent out of an interoffice monitor signal sending circuit 100 to a time-division channel 102, a transmit signal (d) is selected and the contents T of a test time slot are inputted to a shift register 107. The signal contents T circulate by eight bits at every time, so they are sent out to all time slots on a connection bus 110. A receiving circuit 101 selects a signal (f) sent from the channel 102 and a signal (e) sent from a gate 108 through a selector 109. Consequently, the signal contents T are inputted by the receiving circuit 101 at the position of the test time slot. Therefore, the test is taken in normal service without exerting any influence upon other time slots.

5. 发明专利

JPS62202696A TELEVISION SIGNAL GENERATOR 失效
公开(公告)号：JPS62202696A
公开(公告)日：1987-09-07
申请号：JP4408686
申请日：1986-03-03
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： KITAMURA NOBUAKI , NONAKA KAZUNORI , ASAMI HIROYASU
IPC分类号： H04N17/00 , G01R31/28 , G01R31/319
摘要： PURPOSE:To generate a test television signal with simple constitution by accessing a memory storing a television signal according to a counter representing the position of an 1/2 horizontal line and the dot position. CONSTITUTION:A horizontal signal is converted into a signal selecting the kind of a television signal by a conversion memory 3 is correspondence to the position of a 1/2 horizontal line. Various television signal of 1/2 horizontal line are stored in a data storage memory 4, the television signal of 1/2 horizontal line is read from the data storage memory 4 by using the count content of a dot counter 1 and the selection signal converted by the conversion memory to use it as the test television signal.

6. 发明专利

JPS61264935A CONTROL SYSTEM FOR DIGITAL RELAY LINE 失效
公开(公告)号：JPS61264935A
公开(公告)日：1986-11-22
申请号：JP10764385
申请日：1985-05-20
申请人： FUJITSU LTD
发明人： KITAMURA NOBUAKI
IPC分类号： H04J3/16
摘要： PURPOSE:To increase the number of talking channels by providing a band compression decoding means generating digital information and a network means sending digital information having a converted bit rate corresponding to a class or the congenting state of the former digital information. CONSTITUTION:Calls comprising digital information 110A-110N are congested and exceed the normal line capacity of a network means 140, then the network means 140 supplies a part or all the digital information to an LBRCODEC 130. Then the bit rate is converted properly into a value lower than the bit rate of normal coding/decoding depending on the call of the digital information source or the congestion state of the call and the result is sent to a digital relay line 120. When the class of the digital information is high or the degree of congestion is not high, the decrease in the bit rate is reduced and when the class is low and the degree of congestion is high, the decrease in the bit rate is increased. Thus, the quality of the sent digital information has only to be decreased more or less, then the number of the talking channels are increased to prevent the production of call loss.

7. 发明专利

JPS6172429A Error rate measuring device of code transmission line 失效
标题翻译：代码传输线错误率测量装置
公开(公告)号：JPS6172429A
公开(公告)日：1986-04-14
申请号：JP19402584
申请日：1984-09-18
申请人： Fujitsu Ltd
发明人： KITAMURA NOBUAKI
IPC分类号： H03M13/00 , H04J3/14 , H04L1/00
摘要： PURPOSE: To detect easily an erroneous pulse by generating a transmission code from a start clock corresponding to a line at the transmission side, transmitting it while applying format conversion and taking code coincidence detection with the start clock at the reception side.
CONSTITUTION: A code generating circuit 11 of a transmission section 1 of an error rate measuring device uses a clock from an external clock generating source 21 of an interface IF2 to generate one by one bit of an error rate measuring code and it is transmitted to a format FMT converting circuit 22 of the IF2. The circuit 22 converts the input code into a signal FMT on a transmission line 3 and the signal is transmitted to an FMT converting circuit 42 of the IF4 via the transmission line 3. A circuit 42 converts the input signal into an error rate measuring code, which is transmitted to a reception section 5. A synchronizing control circuit 55 of the reception section 5 throws a switch 56 to the position of a comparison pattern generating circuit 52 to apply the input code to the circuit 52. The circuit 52 uses a clock 41 to generate the same code of that of the circuit 11 and when no error exists continuously, it is discriminated that the synchronism is established, the switch 56 is thrown to the position of an error count circuit 57, the input code is compared with the code from the circuit 52 to display (58) the number of errors.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过从对应于发送侧的线路的起始时钟生成发送代码来容易地检测错误脉冲，并在接收侧以开始时钟进行格式转换并进行代码一致检测时发送。构成：错误率测量装置的发送部分1的代码生成电路11使用来自接口IF2的外部时钟生成源21的时钟来生成错误率测量代码的一位，并将其发送到 IF2格式的FMT转换电路22。电路22将输入代码转换为传输线3上的信号FMT，并且该信号经由传输线3发送到IF4的FMT转换电路42.电路42将输入信号转换为错误率测量代码，被发送到接收部分5.接收部分5的同步控制电路55将开关56投到比较模式发生电路52的位置，以将输入的代码施加到电路52.电路52使用时钟41 以产生与电路11相同的代码，并且当连续不存在错误时，判断出同步被建立，将开关56投到错误计数电路57的位置，将输入代码与代码从电路52显示（58）错误的数量。

8. 发明专利

JPS60136495A RECEIVING CIRCUIT OF DIAL PULSE 失效
公开(公告)号：JPS60136495A
公开(公告)日：1985-07-19
申请号：JP24989083
申请日：1983-12-24
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： KITAMURA NOBUAKI , KOGURE KOUJI
IPC分类号： H04Q1/32
摘要： PURPOSE:To enhance flexibility of a receiving logical function by storing various types of status information necessary for a receiving action of a dial pulse in plural addresses as dispersed and by executing renewal logical processing of various types of status information. CONSTITUTION:A dial pulse receiving circuit has a status information holding memory MEM and a general-purpose logical operation circuit group GLG. The general-purpose logical operation circuit group GLG has various general-purpose logical operation circuits such as an adder ADD required when reception processing of a dial pulse is carried out, a gate GA to carry out exclusive OR processing, gates GB and GC to execute AND processing and a gate GD to execute OR processing; a registor REG to accumulate various types of status information read-out from each address of the status information holding memory MEM, gate groups GG1 and GG2 to transmit various types of status information accumulated in the registor REG and to transmit an output of a logical operation circuit to the memory MEM or buffer registors BR1-BR3, and a control holding memory CM.

9. 发明专利

JPS6010820A DRIVING METHOD OF ECHO CANCELLOR 失效
公开(公告)号：JPS6010820A
公开(公告)日：1985-01-21
申请号：JP11696183
申请日：1983-06-30
申请人： FUJITSU LTD
发明人： KITAMURA NOBUAKI , USAMI TAKASHI
IPC分类号： H04B3/23
摘要： PURPOSE:To cancel quickly an echo signal by setting a constant of division obtaining an approximated estimate impulse response correcting amount of an echo cancellor so as to satisfy a prescribed inequality. CONSTITUTION:An input signal (x) from a 4-wire section is fetched in an (x) register 17 and a time series signal xj of the signal (x) is inputted to a convolution circuit 18, a multiplier 21 and a square accumulating circuit 23. The circuit 18 applies convolution between the signal xj and an estimated impulse response H'j from an H register 19 and outputs an estimated echo signal y'. The signal y' is subtracted 16 from an actual echo signal (y) and its residual difference ej is inputted to a terminal station 11 and the multiplier 21. The multiplier 21 inputs the result of multiplication among signals e, xj and correcting coefficient alpha to a shift register 22. A (k) discriminating circuit 24 discriminates a (k) satisfying an inequality from a signal ¦xj¦ from the circuit 23 and the coefficient alpha, a control circuit 25 shifts the register 22 by k-bit by using the (k), outputs an approximated value DELTAH'j of an estimated impulse response correcting amount and inputs the value to an adder 26. The adder 26 adds the signals H'j and DELTAH'j and outputs an impulse response H'j+1 at next time.

10. 发明专利

JPS59134935A Multiplex receiving circuit of serial code 失效
标题翻译：串行码多路复用接收电路
公开(公告)号：JPS59134935A
公开(公告)日：1984-08-02
申请号：JP953083
申请日：1983-01-24
申请人： Fujitsu Ltd
发明人： KITAMURA NOBUAKI , SATOU HIROAKI
IPC分类号： H03M9/00 , H04J3/00 , H04J3/02 , H04J3/04 , H04L5/22
CPC分类号： H04J3/00
摘要： PURPOSE:To realize economically a circuit to be controlled simply by receiving a partial code, revising a stored content of the 1st address of a storage section by the partial code, storing the code revised by the partial code transmitted at the last frame to the 2nd address and outputting a code completed at the 2nd address in parallel. CONSTITUTION:When a code bit Cmk of the m-th line arrives, a storage content of an address (m) is read by a write data editing circuit 8 and after it is revised by the Cmk, it is stored in the address (m) sttended with a write signal (w) from a control circuit 13. Thus, the code from the address 0 to the address 127 in a memory 7 is all revised. Then, in a readout time area from a time slot TS0 to TS127 in a frame F7, the circuit 8 completes a new code by revising the 7-th bit D7 of the stored content by arriving code bits C07-C1277. The most significant bit a7 of the address applied via a gate 12 is set to a logical value 1. Thus, the circuit 8 stores the completed code to addresses 128-255(completed code storaging area 72) of the memory 7.
摘要翻译：目的：为了简单地通过接收部分代码来经济地实现要控制的电路，通过部分代码修改存储部分的第一地址的存储内容，将由最后一帧发送的部分代码修改的代码存储到第二个地址并输出在第二地址并行完成的代码。构成：当第m行的代码位Cmk到达时，地址（m）的存储内容由写入数据编辑电路8读取，并且在被Cmk修改之后，存储在地址（m）中）与来自控制电路13的写入信号（w）相对应。因此，存储器7中的地址0到地址127的代码都被修改。然后，在帧F7中从时隙TS0到TS127的读出时间区域中，电路8通过到达码位C07-C1277修改存储的内容的第7位D7来完成新的代码。经由门12施加的地址的最高有效位a7被设置为逻辑值1.因此，电路8将完成的代码存储到存储器7的地址128-255（完成代码存储区域72）。

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