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1. 发明专利

JPS59229958A MULTIFRAME SYNCHRONOUS TEST SYSTEM 失效
公开(公告)号：JPS59229958A
公开(公告)日：1984-12-24
申请号：JP10413183
申请日：1983-06-13
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： MORI MAKOTO , IWASE YASUMASA , SHIRAISHI YOSHIKATSU , SHIRASAWA SUSUMU , KITAMURA NOBUAKI
IPC分类号： H04J3/14 , H04M3/24 , H04M3/26 , H04Q11/04
摘要： PURPOSE:To classify and assign a trouble occurring to a time-division exchange, to eliminate the need for a communication between controllers, and to simplify a test by facilitating an autonomous test of multiframe synchronism in a digital signal device. CONSTITUTION:When a selection signal (a) is applied to a selection part 106 while a signal (d) is sent out of an interoffice monitor signal sending circuit 100 to a time-division channel 102, a transmit signal (d) is selected and the contents T of a test time slot are inputted to a shift register 107. The signal contents T circulate by eight bits at every time, so they are sent out to all time slots on a connection bus 110. A receiving circuit 101 selects a signal (f) sent from the channel 102 and a signal (e) sent from a gate 108 through a selector 109. Consequently, the signal contents T are inputted by the receiving circuit 101 at the position of the test time slot. Therefore, the test is taken in normal service without exerting any influence upon other time slots.

2. 发明专利

JPS62202696A TELEVISION SIGNAL GENERATOR 失效
公开(公告)号：JPS62202696A
公开(公告)日：1987-09-07
申请号：JP4408686
申请日：1986-03-03
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： KITAMURA NOBUAKI , NONAKA KAZUNORI , ASAMI HIROYASU
IPC分类号： H04N17/00 , G01R31/28 , G01R31/319
摘要： PURPOSE:To generate a test television signal with simple constitution by accessing a memory storing a television signal according to a counter representing the position of an 1/2 horizontal line and the dot position. CONSTITUTION:A horizontal signal is converted into a signal selecting the kind of a television signal by a conversion memory 3 is correspondence to the position of a 1/2 horizontal line. Various television signal of 1/2 horizontal line are stored in a data storage memory 4, the television signal of 1/2 horizontal line is read from the data storage memory 4 by using the count content of a dot counter 1 and the selection signal converted by the conversion memory to use it as the test television signal.

3. 发明专利

JPS60136495A RECEIVING CIRCUIT OF DIAL PULSE 失效
公开(公告)号：JPS60136495A
公开(公告)日：1985-07-19
申请号：JP24989083
申请日：1983-12-24
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： KITAMURA NOBUAKI , KOGURE KOUJI
IPC分类号： H04Q1/32
摘要： PURPOSE:To enhance flexibility of a receiving logical function by storing various types of status information necessary for a receiving action of a dial pulse in plural addresses as dispersed and by executing renewal logical processing of various types of status information. CONSTITUTION:A dial pulse receiving circuit has a status information holding memory MEM and a general-purpose logical operation circuit group GLG. The general-purpose logical operation circuit group GLG has various general-purpose logical operation circuits such as an adder ADD required when reception processing of a dial pulse is carried out, a gate GA to carry out exclusive OR processing, gates GB and GC to execute AND processing and a gate GD to execute OR processing; a registor REG to accumulate various types of status information read-out from each address of the status information holding memory MEM, gate groups GG1 and GG2 to transmit various types of status information accumulated in the registor REG and to transmit an output of a logical operation circuit to the memory MEM or buffer registors BR1-BR3, and a control holding memory CM.

4. 发明专利

JPS5812421A DUTY CORRECTING CIRCUIT 失效
公开(公告)号：JPS5812421A
公开(公告)日：1983-01-24
申请号：JP10936181
申请日：1981-07-15
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： HIROSE KAZUTO , IWASE YASUMASA , KAWAGUCHI MASAHARU , TAKEUCHI WATARU , KITAMURA NOBUAKI
IPC分类号： H03K5/04 , F23N5/00 , H03K5/06
摘要： PURPOSE:To easily reproduce an accurate 50% duty waveform, by using a delay circuit, an FF circuit, and a differentiating circuit in combination. CONSTITUTION:An input signal (a) with a period T supplied from an input terminal 1 has been differentiated of rise by a differentiating circuit 7 to obtain a differential output (b). This differential output (b) sets a D type FF circuit 6 directly. The input signal (a) is further supplied to a delay circuit 3, where it is delayed accurately by T/2 to obtain a delay output (c). Then, a rising edge of this delay output (c) resets the FF circuit 6. Therefore, the circuit 6 is set and reset repeatedly, so that the FF circuit 6 outputs a 50% duty rectangular wave, which has the same frequency with the input signal (a) to an output terminal 5. Thus, the accurate 50% duty waveform is reproduced easily.

5. 发明专利

JPS607236A CODE COMPRESSING CIRCUIT 失效
公开(公告)号：JPS607236A
公开(公告)日：1985-01-16
申请号：JP11439783
申请日：1983-06-27
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： KAWAGUCHI MASAHARU , IWASE YASUMASA , FUKUI AKIRA , MIE HISAKI , KITAMURA NOBUAKI
IPC分类号： H04B14/04
摘要： PURPOSE:To attain a simple circuit constitution, short converting time and large degree of multiplex by inputting an output of an ROM to a register only when a logical product of a logical sum in n-bit in the present input and a logical sum being a value representing the location in a stored word is established so as to obtain a register output to be used as a desired compressing code at the time point of the end of input of one word. CONSTITUTION:An output of a counter (not shown), output of an adder 203, and an output of the adder 203 after passing through a D-FF205 (an output of the adder 203 before one clock) are supplied to an address of an ROM208, and a 7-bit being a content of the ROM208 and an output being a code bit 222 of an absolute value circuit 202 are fed to a register 207 via an NOT circuit 206. The condition that the register 207 fetches a data is only that a logical product 213 between an output of a logical sum 214 of an output 4-bit of the adder 203 and a logical sum 212 of an output 2-bit of a counter from an input terminal 210 is established. It is required that the content of the ROM208 is written in advance. In such a way, the output of the register 207 after the most significant 4-bit of a linear code is inputted is obtained as an effective compressing code.

6. 发明专利

JPS58151195A DISTRIBUTING SYSTEM OF TIME DIVISION MULTIPLEX CHANNEL 失效
公开(公告)号：JPS58151195A
公开(公告)日：1983-09-08
申请号：JP3422382
申请日：1982-03-04
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD
发明人： KITAMURA NOBUAKI , IWASE YASUMASA , MURAKAMI SUEO , SHIRASAWA SUSUMU , MORI MAKOTO
IPC分类号： H04Q3/52 , H04Q11/04
摘要： PURPOSE:To fix wirings of time division multiplex channel for distribution in a conventional device, by distributing a time slot included in the time division multiplex channel to an arbitrary function circuit with a time switch. CONSTITUTION:A time division network 1 is connected with plural channel highways 2 and signal highways 3-6 connected to a signal device 7. The highways 3-6 are divided into four time slot groups having 8 time slots equally and each time slot group is assigned to each function circuit as shown in Figure. An interface circuit 16 of the signal device 7 is provided with a time switch 26. Since each time slot group of the highways 3-6 is distributed into arbitrary distributing highways 27-36 with the time switch 26 provided for the interface circuit 16 in the signal device 7, even if the highways 27-36 are wired fixedly, an arbitrary time slot group is distributed into a required function circuit.

7. 发明专利

JPS6076858A RINGING TONE-BASED MEMORY CIRCUIT 失效
公开(公告)号：JPS6076858A
公开(公告)日：1985-05-01
申请号：JP18554183
申请日：1983-10-04
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： KITAMURA NOBUAKI , TSUBOI TOSHINORI
IPC分类号： H04M3/02 , H04M19/02
摘要： PURPOSE:To save the memory capacity of a ringing tone-based memory circuit by producing a compound code having a reduced number of codes from the information which discriminates the type and the phase of the ringing tone and storing this produced code. CONSTITUTION:The type-based information ri of three bits which designates a ringing the tone is transmitted to a coder 7 together with the phase information Pi of two bits transmitted from a phase information generating circuit 2. The coder 7 compounds both information ri and Pi to obtain a compound code si of four bits. This code si is stored by a ringing tone-based memory circuit 11. The circuit 11 delivers periodically a compound code so in responding with telephone sets 61-6n respectively. A decoder 8 delivers the code so after ecoding and separating it into the type-based information ro and phase information po. A rigning tone transmission control circuit 3 controls ringing tone intermitting contacts 41-4n on a basis of both information ro and po and produces the ringing tone at each telephone set.

8. 发明专利

JPS58139540A FRAME SYNCHRONISM PROTECTING CIRCUIT 失效
公开(公告)号：JPS58139540A
公开(公告)日：1983-08-18
申请号：JP2235382
申请日：1982-02-15
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD
发明人： KITAMURA NOBUAKI , IWASE YASUMASA , SHIRAISHI YOSHIKATSU , TAKEUCHI WATARU , MORI MAKOTO
IPC分类号： H04J3/06 , H04L7/08
摘要： PURPOSE:To obtain an economical frame synchronism protecting circuit using a digital circuit, by protecting the frame synchronism with lock-in in case coincidence/discordance pulses are produced more than the threshold level within a prescribed frame period. CONSTITUTION:A control circuit 7 sends a signal to a coincidence/discordance circuit 1 and then transmits a coincidence pulse when the coincidence is obtained between the circuit data fed through a terminal 9 and a frame synchronous pattern supplied from a synchronous pattern generating circuit 2. Then the coincidence pulses at the specific position of each frame are counted by a counting circuit 3 which is reset with an 8-frame period. When the count value of the circuit 3 exceeds the threshold level given from a threshold level generating circuit 5, an output of comparison is delivered. Receiving this output, the circuit 7 decides that the lock-in is over and then feeds signals to the circuits 1 and 5. Then the discordance pulse is generated from the circuit 1. When the count value of the circuit 3 exceeds the threshold level of the circuit 5, the generation of step out is decided. Then coincidence pulses are transmitted from the circuits 1 and 5.

9. 发明专利

JPS57143992A TRANSMITTING AND RECEIVING CIRCUIT FOR DIGITAL SIGNAL 失效
公开(公告)号：JPS57143992A
公开(公告)日：1982-09-06
申请号：JP2840381
申请日：1981-03-02
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： KAWAGUCHI MASAHARU , IWASE YASUMASA , FUKUI AKIRA , TOKUNAGA KAORU , KITAMURA NOBUAKI
IPC分类号： H04M3/32 , H04M3/26 , H04M7/00 , H04Q1/44 , H04Q1/45 , H04Q11/04
摘要： PURPOSE:To reduce time slots and circuits in number by providing a memory area for mode holding, and by adapting all time slots to any function by receiving and holding a function switching order for every time slot. CONSTITUTION:Under the timing control of a timing pulse generating circuit 12, a mode held in a mode holding memory 202 is read out and according to the mode, a coefficient generating circuit 8 and a threshold-value generating circuit 9 are controlled to perform respective operations successively. Through transmitting operation and circuit operation by which an input signal is sent back as it is, the mode held in the memory 202 is read out. According to the read mode, a signal generating circuit 15 is controlled to generate a signal, and then a selector 17 outputs a signal transmission order which is the contents of a memory 13, and an output from corresponding one of a shift register 14, the signal generating circuit 15, and a non-calling pattern generating circuit 16 to an output terminal according to the mode held in the memory 202.

10. 发明专利

JPS62206959A MULTIPLEX ANNOUNCEMENT EQUIPMENT 失效
公开(公告)号：JPS62206959A
公开(公告)日：1987-09-11
申请号：JP4901286
申请日：1986-03-06
申请人： FUJITSU LTD
发明人： KITAMURA NOBUAKI
IPC分类号： H04M3/50
摘要： PURPOSE:To listen to an announcement message from the beginning by providing a voice memory storing plural announcement messages to each address and a multiplex address control circuit transmitting an announcement address for transmitting the required announcement message to a voice memory. CONSTITUTION:When a subscriber 8 gives a call, a central controller 10 connects the subscriber 8 via an exchange switch 9 to one of multiplex channels of a signal highway 4 to a send a high-order announcement address representing the announcement message kind to a multiplex address control circuit 2. The control circuit 2 uses a reset circuit to reset a low-order announcement address representing voice sample data to be set at the point of time to the start address and sends the result to a voice memory 1. The voice memory 1 uses the announcement address to send a required announcement message. The control circuit 2 steps the start address of the low-order announcement address to send a new address to the voice memory 1 one after another to transmit the announcement message to the subscriber 8 continuously.

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