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1. 发明专利

JP2014099643A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2014099643A
公开(公告)日：2014-05-29
申请号：JP2014008160
申请日：2014-01-20
申请人： Fuji Electric Co Ltd , 富士電機株式会社
发明人： NEMOTO MICHIO , YOSHIMURA TAKASHI
IPC分类号： H01L29/868 , H01L21/329 , H01L21/336 , H01L29/06 , H01L29/739 , H01L29/78 , H01L29/861
CPC分类号： H01L29/0611 , H01L21/263 , H01L21/268 , H01L21/3221 , H01L29/06 , H01L29/0684 , H01L29/0804 , H01L29/0821 , H01L29/1004 , H01L29/1095 , H01L29/32 , H01L29/36 , H01L29/66348 , H01L29/7393 , H01L29/7397 , H01L29/861 , H01L29/868 , H01L29/885
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can reduce variation in withstanding voltage and variation in switching characteristics and reduce manufacturing cost.SOLUTION: A semiconductor device comprises: a p anode layer 2 formed on one principal surface side of an ndrift layer 1; an ncathode layer 3 formed on the other surface side; an anode electrode 4 formed on a surface of the p anode layer 2; a cathode electrode 5 formed on a surface of the ncathode layer 3; and n-type broad buffer regions 6 each of which has a net doping concentration higher than an impurity concentration of a bulk of a wafer and lower than a net doping concentration of each of the ncathode layer 3 and the p anode layer 2, and which are formed inside the ndrift layer 1. A relationship between specific resistance ρof the ndrift layer 1 and a rated voltage Vsatisfies 0.12 V≤ρ≤0.25 V. In addition, a total amount of the net doping concentrations of the broad buffer regions 6 is not less than 4.8×10atoms/cmand not more than 1.0×10atoms/cm.
摘要翻译：要解决的问题：提供一种半导体器件，其能够降低耐受电压的变化和开关特性的变化，并降低制造成本。解决方案：半导体器件包括：形成在n型层1的一个主表面侧的p阳极层2; 形成在另一个表面侧的阴极层3; 形成在p阳极层2的表面上的阳极电极4; 形成在阴极层3的表面上的阴极电极5; 和n型宽缓冲区域6，其各自的净掺杂浓度高于晶片本体的杂质浓度并且低于阴极层3和p阳极层2中的每一个的净掺杂浓度，并且其中形成在n型层1内。n型层1的电阻率rgr与额定电压Vs之间的关系满足0.12V≤＆rgr≤0.25V。此外，宽缓冲区域的净掺杂浓度的总量 6不小于4.8×10原子/厘米，不大于1.0×10原子/厘米2。

2. 发明专利

JP2013077833A Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：JP2013077833A
公开(公告)日：2013-04-25
申请号：JP2012275428
申请日：2012-12-18
申请人： Fuji Electric Co Ltd , 富士電機株式会社
发明人： YOSHIMURA TAKASHI , TAKACHI TAKUMI
IPC分类号： H01L21/336 , H01L29/739 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which can achieve excellent ohmic contact by preventing contamination on a rear face side caused by creeping diffusion from a front face side without requiring a complicated process even when the manufacturing method includes a process of thinning a semiconductor substrate by grinding the rear face and a diffusion layer formation process requiring at least a heating treatment in a range of 700°C-950°C on the rear face side after forming an impurity diffusion layer on a surface of the semiconductor substrate.SOLUTION: A semiconductor substrate manufacturing method comprises: thinning a semiconductor substrate 1 after forming at least an n-type impurity diffusion layer 3 on one surface of the semiconductor substrate 1; and subsequently forming on both sides of the semiconductor substrate, before a process of forming a p-type impurity diffusion layer 9 including a process of forming a diffusion layer 7 in which ion implantation and a heating treatment having a temperature profile from 700°C to 950°C are performed on the rear face side, oxide films each having a thickness such that a peak of an n-type impurity concentration distribution caused by creeping diffusion from a surface side does not at least penetrate the oxide film.
摘要翻译：解决的问题：提供一种半导体器件制造方法，其可以通过防止由正面侧的蠕变扩散引起的背面污染而实现优异的欧姆接触，而不需要复杂的工艺，即使当制造方法包括在半导体衬底的表面上形成杂质扩散层之后，通过研磨后表面来减薄半导体衬底的方法以及需要至少在700℃-950℃范围内的加热处理的扩散层形成工艺半导体衬底。解决方案：半导体衬底制造方法包括：在半导体衬底1的一个表面上至少形成n型杂质扩散层3之后，使半导体衬底1变薄; 在形成包括形成扩散层7的工序的p型杂质扩散层9的工序之前，在半导体衬底的两面上形成离子注入和具有700℃〜在背面侧进行950℃的氧化膜，其厚度使得由表面侧的蠕变扩散引起的n型杂质浓度分布的峰值至少不透过氧化膜。版权所有（C）2013，JPO＆INPIT

3. 发明专利

JP2002314083A SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2002314083A
公开(公告)日：2002-10-25
申请号：JP2002030282
申请日：2002-02-07
申请人： FUJI ELECTRIC CO LTD
发明人： OTSUKI MASATO , MOMOTA SEIJI , KIRISAWA MITSUAKI , YOSHIMURA TAKASHI
IPC分类号： H01L29/78 , H01L29/739
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device constituting an IGBT that can be manufactured at good yield by the use of an inexpensive wafer and has little loss. SOLUTION: In an IGBT manufactured by the use of a wafer that is cut out of a polished and cleaned ingot, for example, a FZ wafer, an n-type impurity diffusion layer having a quantity of dose enough to stop an electric field at an OFF timing is formed, between a collector 9 and a base layer 2, as a field stop layer 24 for stopping the electric field at the OFF timing such that, assuming that a position where the impurity concentration of the field stop layer 24 is two times the impurity concentration of the base layer 2 be Xfs and a bonding position where the field stop layer 24 is bonded to the collector layer 9 be Xj, a value of (Xfs-Xj) ranges from 0.5 μm to 3 μm.

4. 发明专利

JP2002314084A METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2002314084A
公开(公告)日：2002-10-25
申请号：JP2002030283
申请日：2002-02-07
申请人： FUJI ELECTRIC CO LTD
发明人： OTSUKI MASATO , MOMOTA SEIJI , KIRISAWA MITSUAKI , YOSHIMURA TAKASHI
IPC分类号： H01L29/78 , H01L21/336 , H01L29/739
摘要： PROBLEM TO BE SOLVED: To manufacture a semiconductor device constituting an IGBT of little loss by the use of an inexpensive wafer at good yield. SOLUTION: After an emitter electrode 5 is formed, a principal surface on an opposite side is polished to a predetermined thickness to make a center line average roughness Ra of a polished surface 1 μm or less and a filtered wave at the center line Wca 10 μm or less. Only the polished surface is selectively cleaned with a chemical to remove particles and then, in order to form a field stop layer 24, phosphorus ions are implanted into the cleaned surface by an ion implanting method, and then, in order to form a collector layer 9, boron irons are implanted by the ion implanting method. The wafer is put in a diffusion furnace and is subjected to heat treatment at a temperature from 300 deg.C to 550 deg.C to form the field stop layer 24 and the collector 9, and then a collector electrode 10 is formed. A portion contacting the semiconductor of the collector electrode 10 is made of aluminum or platinum 0.3 μm or thicker.

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