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1. 发明专利

JP2013247252A Silicon carbide semiconductor device and method of manufacturing the same 有权
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：JP2013247252A
公开(公告)日：2013-12-09
申请号：JP2012120263
申请日：2012-05-25
申请人： National Institute Of Advanced Industrial & Technology , 独立行政法人産業技術総合研究所 , Fuji Electric Co Ltd , 富士電機株式会社
发明人： TANAKA ATSUYUKI , IWAMURO NORIYUKI , HARADA SHINSUKE
IPC分类号： H01L29/78 , H01L21/336 , H01L29/12 , H01L29/739
CPC分类号： H01L29/7802 , H01L21/046 , H01L29/045 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/1608 , H01L29/4238 , H01L29/66068 , H01L29/66325 , H01L29/66712 , H01L29/7395
摘要： PROBLEM TO BE SOLVED: To obtain reliability to reduce on-resistance without causing damage to a gate oxide film even in high voltage application.SOLUTION: A silicon carbide semiconductor device comprises: a first conductivity type semiconductor substrate 1; a first conductivity type semiconductor layer 2 which is formed on the semiconductor substrate 1 and has a low impurity concentration; a second conductivity type semiconductor layer 2 which is selectively formed on the first conductivity type semiconductor layer 2 and has a high impurity concentration; a second conductivity type base layer 4 which is formed on a surface of the second conductivity type semiconductor layer 3 and has a low impurity concentration; a first conductivity type source region 7 selectively formed in a surface layer of the base layer 4; a first conductivity type well region 6 formed so as to penetrate the base layer 4 from a surface to reach the first conductivity type semiconductor layer 2; and a gate electrode 9 formed via a gate insulation film on a surface of the base layer 4 sandwiched between the source region 7 and the well region 6. Portions of the second conductivity type semiconductor layers 3 in different cells are connected with each other by a connection portion 3a in a region under the well region 6.
摘要翻译：要解决的问题：即使在高电压应用中，也可以获得降低导通电阻而不会对栅极氧化膜造成损害的可靠性。解决方案：一种碳化硅半导体器件包括：第一导电型半导体衬底1; 形成在半导体衬底1上并具有低杂质浓度的第一导电类型半导体层2; 第二导电型半导体层2，其被选择性地形成在第一导电类型半导体层2上并且具有高杂质浓度; 形成在第二导电型半导体层3的表面上并具有低杂质浓度的第二导电型基极层4; 选择性地形成在基底层4的表面层中的第一导电型源极区域7; 形成为从表面贯穿基层4到达第一导电型半导体层2的第一导电型阱区域6; 以及在基极层4的夹在源极区域7和阱区域6之间的基极层4的表面经由栅极绝缘膜形成的栅极电极9.不同电池单元中的第二导电型半导体层3的一部分通过连接部分3a在阱区域6下方。

2. 发明专利

JP2013251407A Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device 审中-公开
标题翻译：硅碳化硅半导体器件及制造碳化硅半导体器件的方法
公开(公告)号：JP2013251407A
公开(公告)日：2013-12-12
申请号：JP2012125255
申请日：2012-05-31
申请人： National Institute Of Advanced Industrial & Technology , 独立行政法人産業技術総合研究所 , Fuji Electric Co Ltd , 富士電機株式会社
发明人： TSUJI TAKASHI , IWAMURO NORIYUKI , FUKUDA KENJI
IPC分类号： H01L29/47 , H01L21/329 , H01L29/872
CPC分类号： H01L29/1608 , H01L21/02529 , H01L24/05 , H01L29/0615 , H01L29/417 , H01L29/66143 , H01L29/872 , H01L2924/13055 , H01L2924/13091 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device that allows reducing a region of a withstand-voltage structure portion, enlarging an active region, and being easily manufactured, and to provide a method of manufacturing the silicon carbide semiconductor device.SOLUTION: In a surface layer of a silicon carbide substrate base, a p-type region 3, a p-type region 4, and a p-type region 5 are provided, and these regions constitute an element structure of a Schottky junction provided in a withstand-voltage structure portion surrounding an active region. The p-type region 5 surrounds the p-type region 3 and the p-type region 4, and constitutes a junction termination (JTE) structure. A Schottky electrode 7 forms a Schottky junction with an n-type silicon carbide epitaxial layer 2. End portions of the Schottky electrode 7 and an electrode pad 8 are located above the p-type region 3, and an end portion 7a of the Schottky electrode 7 is exposed from an end portion 8a of the electrode pad 8.
摘要翻译：要解决的问题：提供一种能够减小耐压结构部分的区域，扩大有源区域并容易制造的碳化硅半导体器件，并提供一种制造碳化硅半导体器件的方法。解决方案：在碳化硅基板的表面层中，设置有p型区域3，p型区域4和p型区域5，这些区域构成肖特基结的元件结构， - 围绕有源区域的电压结构部分。 p型区域5围绕p型区域3和p型区域4，并且构成结终端（JTE）结构。肖特基电极7与n型碳化硅外延层2形成肖特基结。肖特基电极7和电极焊盘8的端部位于p型区域3的上方，肖特基电极的端部7a 7从电极焊盘8的端部8a露出。

3. 发明专利

JP2013232562A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2013232562A
公开(公告)日：2013-11-14
申请号：JP2012104230
申请日：2012-04-27
申请人： National Institute Of Advanced Industrial & Technology , 独立行政法人産業技術総合研究所 , Fuji Electric Co Ltd , 富士電機株式会社
发明人： IWAMURO NORIYUKI , HOSHI YASUYUKI , HARADA YUICHI , HARADA SHINSUKE
IPC分类号： H01L29/06 , H01L21/336 , H01L29/12 , H01L29/78
CPC分类号： H01L29/1608 , H01L29/0615 , H01L29/0661 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/66068 , H01L29/7395 , H01L29/78 , H01L29/7811 , H01L29/8611 , H01L29/872
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which has an element structure stably exhibiting high voltage withstanding characteristics and which has low on-resistance.SOLUTION: A semiconductor device comprises: an active region 100a including a pregion 3 which is selectively provided on a surface layer of an ndrift layer 2 on an nsemiconductor substrate 1; a p base layer 4 provided on surfaces of the ndrift layer 2 and the pregion 3; a MOS structure provided in the p base layer 4; and a pregion 33 provided on the pregion 3 at a part of the active region 100a where the MOS structure is not formed. The pregion 33 contacts a source electrode 10. The semiconductor device comprises a voltage withstanding structure region 100b in which a JTE structure 13 composed of at least a pregion 21 is provided so as to surround the active region 100a. The JTE structure 13 is provided away from the pregion 3 and the p base layer 4. In addition, the pregion 21 contacts the pregion 33 at a part near a border between the active region 100a and the voltage withstanding structure region 100b where the MOS structure is not formed.
摘要翻译：要解决的问题：提供一种半导体器件，其具有稳定地呈现高耐压特性并且具有低导通电阻的元件结构。半导体器件包括：有源区域100a，其包括选择性地设置在半导体衬底1上的n层层2的表面层; 设置在n层2和前摄体3的表面上的p基层4; 设置在p基层4中的MOS结构; 以及在没有形成MOS结构的有源区域100a的一部分处设置在前摄体3上的前摄体33。前置电极33接触源电极10.半导体器件包括电压承受结构区域100b，其中设置有由至少前导件21构成的JTE结构13，以围绕有源区域100a。 JTE结构13远离前摄体3和p基底层4设置。此外，前置电极21在有源区域100a和耐压结构区域100b之间的边界附近的部分处接触前置电极33，其中MOS结构没有形成。

4. 发明专利

JP2013211440A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2013211440A
公开(公告)日：2013-10-10
申请号：JP2012081171
申请日：2012-03-30
申请人： National Institute Of Advanced Industrial & Technology , 独立行政法人産業技術総合研究所 , Fuji Electric Co Ltd , 富士電機株式会社
发明人： HARADA YUICHI , IWAMURO NORIYUKI , HOSHI YASUYUKI , HARADA SHINSUKE
IPC分类号： H01L29/78 , H01L29/12
CPC分类号： H01L29/7827 , H01L21/049 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/42372 , H01L29/42376 , H01L29/4238 , H01L29/66068 , H01L29/7802
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that improves the dielectric breakdown strength and reliability of an insulating film while maintaining the primary functions as a MOSFET.SOLUTION: A stack in which an N-type SiC layer 2 is formed on a surface of an N-type SiC substrate 1 is used as a basic layer, P-type regions 3 are formed on a surface of the N-type SiC layer 2, and N-type source regions 4 are formed on surfaces of the P-type regions 3. Source electrodes 8 are formed on surfaces of the N-type source regions 4, and a drain electrode 9 is formed on a rear surface side (the other surface side) of the N-type SiC substrate 1. Gate electrodes 7 are formed only on the surfaces of the P-type regions 3 via gate insulating films (oxide films) 6. The configuration eliminates the application of a high voltage between the drain electrode 9 and the gate electrodes 7 due to, such as, the stop of the voltage application to the gate electrodes 7, thereby eliminating the application of a large electric field to the gate insulating films 6.
摘要翻译：要解决的问题：提供一种提高绝缘膜的介电击穿强度和可靠性的半导体器件，同时保持主要功能作为MOSFET。解决方案：在其表面上形成N型SiC层2的堆叠使用N型SiC衬底1作为碱性层，在N型SiC层2的表面上形成有P型区3，在P型区的表面形成有N型源极区4 源极电极8形成在N型源极区域4的表面上，并且在N型SiC衬底1的后表面侧（另一个表面侧）形成漏电极9.形成栅电极7 仅通过栅极绝缘膜（氧化物膜）6在P型区域3的表面上。这种构造消除了由于诸如停止了漏极电极9而导致的漏电极9和栅电极7之间的高电压的施加。施加到栅电极7，从而消除了应用对栅极绝缘膜6的大电场的离子。

5. 发明专利

JP2013211447A Silicon carbide vertical mosfet and manufacturing method of the same 有权
标题翻译：硅碳化钨垂直MOSFET及其制造方法
公开(公告)号：JP2013211447A
公开(公告)日：2013-10-10
申请号：JP2012081429
申请日：2012-03-30
申请人： National Institute Of Advanced Industrial & Technology , 独立行政法人産業技術総合研究所 , Fuji Electric Co Ltd , 富士電機株式会社
发明人： IWAMURO NORIYUKI , HARADA SHINSUKE , HOSHI YASUYUKI , HARADA YUICHI
IPC分类号： H01L29/12 , H01L21/336 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To achieve both of improvement in element withstanding voltage and reduction in on-resistance at the same time by generating a depletion layer at a joint surface between a drift layer which is an n-type withstanding voltage region and a high-concentration p-type layer even when an impurity concentration of the drift layer of the silicon carbide vertical MOSFET is increased.SOLUTION: A silicon carbide vertical MOSFET comprises: a first conductivity type well region selectively formed on a surface of a substrate 1; an interlayer insulation film 13 which is formed via a gate insulation film 8 and a gate poly-Si electrode 9, on at least a part of a surface exposed part of a second conductivity type third semiconductor layer 21 sandwiched between a first conductivity type source region 5 and the first conductivity type well region; a source electrode 10 which contacts surfaces of the first conductivity type source region 5 and the third semiconductor layer 21 in common; and a drain electrode 11 formed on a rear face of the silicon carbide substrate 1. At least one layer of high-concentration and second conductivity type semiconductor layers 3, 31 is formed inside the first semiconductor layer 2 on the same position.
摘要翻译：要解决的问题为了同时通过在作为n型耐压区域的漂移层和高压电极之间的接合面处产生耗尽层来实现元件耐受电压的提高和导通电阻的降低，即使当碳化硅垂直MOSFET的漂移层的杂质浓度增加时，浓度p型层也增加。解决方案：碳化硅垂直MOSFET包括：选择性地形成在衬底1的表面上的第一导电类型阱区; 在第二导电类型的第三半导体层21的表面暴露部分的至少一部分上夹着第一导电类型的源极区域和第二导电类型的源极区域之间经由栅极绝缘膜8和栅极多晶硅电极9形成的层间绝缘膜13 5和第一导电类型井区; 与第一导电型源极区域5和第三半导体层21的表面共同接触的源电极10; 以及形成在碳化硅衬底1的背面上的漏电极11.至少一层高浓度和第二导电类型半导体层3,31在第一半导体层2的内部形成在同一位置上。

6. 发明专利

JP2013232557A Silicon carbide semiconductor element manufacturing method 有权
标题翻译：硅碳化硅半导体元件制造方法
公开(公告)号：JP2013232557A
公开(公告)日：2013-11-14
申请号：JP2012104224
申请日：2012-04-27
申请人： National Institute Of Advanced Industrial & Technology , 独立行政法人産業技術総合研究所 , Fuji Electric Co Ltd , 富士電機株式会社
发明人： FUKUDA KENJI , IWAMURO NORIYUKI , GOTO MASAHIDE
IPC分类号： H01L21/28
摘要： PROBLEM TO BE SOLVED: To form an ohmic electrode which can ensure adhesion of the electrode by inhibiting release of carbon while ensuring an ohmic property.SOLUTION: A silicon carbide semiconductor element manufacturing method comprises a process of forming a contact electrode on a silicon carbide substrate 1. In the process of forming the contact electrode, metal (pure metal or alloy which includes any one or more among titanium, zirconium and hafnium) which easily generates carbide and also easily generates nitride is used as an electrode chief material of the contact electrode and thermal annealing is performed in an atmosphere consisting primarily of nitrogen thereby to convert in thermal annealing, the metal in the electrode material of the contact electrode in a region of a contact hole 9 where the silicon carbide substrate 1 and the metal in the contact electrode material directly contact each other to a mixed layer 12 which includes both of carbide and nitride.
摘要翻译：要解决的问题：形成欧姆电极，其可以通过抑制碳的释放来确保电极的粘附，同时确保欧姆性能。解决方案：碳化硅半导体元件制造方法包括在碳化硅衬底上形成接触电极的工艺在形成接触电极的过程中，使用易于生成碳化物并且容易产生氮化物的金属（包括钛，锆和铪中的任何一种或多种的纯金属或合金）用作接触电极的电极主要材料并且在主要由氮气组成的气氛中进行热退火，从而在热退火中将接触电极的电极材料中的金属在接触孔9的区域中转化，其中碳化硅衬底1和接触电极中的金属材料直接彼此接触到包括碳化物和氮化物两者的混合层12。

7. 发明专利

JP2013211460A High-voltage semiconductor device 有权
标题翻译：高断电压半导体器件
公开(公告)号：JP2013211460A
公开(公告)日：2013-10-10
申请号：JP2012081736
申请日：2012-03-30
申请人： National Institute Of Advanced Industrial & Technology , 独立行政法人産業技術総合研究所 , Fuji Electric Co Ltd , 富士電機株式会社
发明人： IWAMURO NORIYUKI , HARADA SHINSUKE , HOSHI YASUYUKI , HARADA YUICHI
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L29/12 , H01L29/47 , H01L29/872
CPC分类号： H01L29/1095 , H01L21/046 , H01L21/049 , H01L29/045 , H01L29/0619 , H01L29/0661 , H01L29/0878 , H01L29/1608 , H01L29/6606 , H01L29/66068 , H01L29/7811 , H01L29/868 , H01L29/872
摘要： PROBLEM TO BE SOLVED: To improve a breakdown strength with low on-resistance while a sufficient element breakdown voltage characteristic is held for a process variation at the time of ion implantation in a peripheral breakdown voltage structure, independent of crystal plane direction of a substrate.SOLUTION: A vertical high breakdown voltage semiconductor device includes a first conductive type semiconductor substrate (1), a semiconductor layer (2) which is formed on the semiconductor substrate (1) to be first conductivity type and has concentration lower than the semiconductor substrate (1), a second conductivity type semiconductor layer (3) of high concentration which is selectively formed on the surface of the semiconductor layer (2), a base layer (4) of second conductivity type and low concentration, formed on the semiconductor layer (2) and the second conductivity type semiconductor layer (3), and a first conductive type source region (5) which is selectively formed on a surface layer of the base layer (4). At an element peripheral part, a part of the second conductivity type semiconductor layer (3) is removed, and then, on the surface of the semiconductor layer (2) whose concentration is lower than the semiconductor substrate (1), a plurality of second conductivity type layers (11 and 12) of low concentration are formed. The second conductivity type layer (11) at the innermost periphery is arranged not to contact to the second conductivity type semiconductor layer (3) and the base layer (4).
摘要翻译：要解决的问题：为了在外围击穿电压结构中的离子注入时保持足够的元件击穿电压特性，而与基板的晶面方向无关，提高具有低导通电阻的击穿强度。解决方案：垂直高击穿电压半导体器件包括第一导电类型半导体衬底（1），半导体衬底（1）上形成为第一导电类型并具有比半导体衬底低的浓度的半导体层（2） 1），在半导体层（2）的表面上选择性地形成有高浓度的第二导电型半导体层（3），形成在半导体层（2）上的第二导电型和低浓度的基极层（4） 2）和第二导电类型半导体层（3）以及选择性地形成在表面l上的第一导电型源极区域（5）基层（4）。在元件周边部分，去除第二导电类型半导体层（3）的一部分，然后在其半导体层（2）的表面上浓度低于半导体衬底（1）的多个第二形成低浓度的导电型层（11和12）。最外围的第二导电类型层（11）布置成不与第二导电类型半导体层（3）和基底层（4）接触。

8. 发明专利

JP2013251406A Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device 有权
标题翻译：硅碳化硅半导体器件及制造碳化硅半导体器件的方法
公开(公告)号：JP2013251406A
公开(公告)日：2013-12-12
申请号：JP2012125254
申请日：2012-05-31
申请人： National Institute Of Advanced Industrial & Technology , 独立行政法人産業技術総合研究所 , Fuji Electric Co Ltd , 富士電機株式会社
发明人： TSUJI TAKASHI , KINOSHITA AKIMASA , IWAMURO NORIYUKI , FUKUDA KENJI
IPC分类号： H01L29/47 , H01L29/41 , H01L29/872
CPC分类号： H01L29/872 , H01L21/02529 , H01L29/0615 , H01L29/0619 , H01L29/08 , H01L29/1608 , H01L29/36 , H01L29/47 , H01L29/66143
摘要： PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device that allows sufficiently enlarging a forward current and improving the withstand voltage, and to provide a method of manufacturing the silicon carbide semiconductor device.SOLUTION: In a surface layer of a silicon carbide substrate base, a p-type region 3, a p-type region 4, and p-type regions 5 are selectively provided. The p-type region 3 and the p-type region 4 are provided in a withstand-voltage structure portion surrounding an active region. The p-type regions 5 are provided in the active region and constitute a JBS structure. The p-type region 4 surrounds the p-type region 3 and constitutes a junction termination (JTE) structure. A Schottky electrode 7 forms a Schottky junction with an n-type silicon carbide epitaxial layer 2. The Schottky electrode 7 is overhung on an interlayer insulating film 6 covering a part of the p-type region 3, and the overhung portion functions as a field plate. The p-type regions 5 have an acceptor concentration higher than or equal to a predetermined concentration, thereby enlarging a forward surge current.
摘要翻译：要解决的问题：提供一种允许充分扩大正向电流并提高耐电压的碳化硅半导体器件，并提供一种制造碳化硅半导体器件的方法。解决方案：在碳化硅衬底基底的表面层选择性地设置p型区域3，p型区域4和p型区域5。 p型区域3和p型区域4设置在围绕有源区域的耐压结构部分中。 p型区域5设置在有源区域中并构成JBS结构。 p型区域4围绕p型区域3并构成结终端（JTE）结构。肖特基电极7与n型碳化硅外延层2形成肖特基结。肖特基电极7悬空在覆盖p型区域3的一部分的层间绝缘膜6上，并且悬臂部分作为场盘子。 p型区域5具有高于或等于预定浓度的受主浓度，从而扩大正向浪涌电流。

9. 发明专利

JP2013232561A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2013232561A
公开(公告)日：2013-11-14
申请号：JP2012104229
申请日：2012-04-27
申请人： National Institute Of Advanced Industrial & Technology , 独立行政法人産業技術総合研究所 , Fuji Electric Co Ltd , 富士電機株式会社
发明人： HARADA SHINSUKE , IWAMURO NORIYUKI , HOSHI YASUYUKI , HARADA YUICHI
IPC分类号： H01L29/78 , H01L29/12
CPC分类号： H01L29/1608 , H01L29/0873 , H01L29/0878 , H01L29/36 , H01L29/78 , H01L29/7802
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can improve insulation breakdown resistance of a gate insulation film and improve reliability of the gate insulation film.SOLUTION: A semiconductor device comprises: an n type SiC layer formed on a surface of an ntype SiC substrate; a plurality of p type regions selectively formed inside the n type SiC layer; a p type SiC layer formed across surfaces of the n type SiC layer and the p type regions; an n type region formed inside the p type SiC layer so as to connect to the n type SiC layer; and an ntype source region and a ptype contact region which are formed inside the p type SiC layer in contact with each other and away from the n type region. The n type region is formed such that a width Lof the n type region inside the p type SiC layer is within a range of 0.8 μm-3.0 μm and an impurity concentration of the n type region is within a range of 1.0×10cm-5.0×10cm. Accordingly, a large electric field is not applied to a gate oxide film thereby to improve breakdown resistance of a gate insulation film and improve reliability of the gate insulation film.
摘要翻译：要解决的问题：提供一种可以提高栅极绝缘膜的绝缘击穿电阻并提高栅极绝缘膜的可靠性的半导体器件。解决方案：一种半导体器件包括：形成在n型SiC表面上的n型SiC层基质; 选择性地形成在n型SiC层内的多个p型区; 形成在n型SiC层和p型区域的表面上的p型SiC层; 形成在p型SiC层内的n型区域，以连接到n型SiC层; 以及形成在p型SiC层内部并且彼此接触并远离n型区域的n型源极区域和p型接触区域。 n型区域形成为使p型SiC层内的n型区域的宽度L在0.8μm〜3.0μm的范围内，n型区域的杂质浓度在1.0×10cm〜5.0的范围内 ×10厘米。因此，不向栅极氧化膜施加大的电场，从而提高栅极绝缘膜的耐击穿性，提高栅极绝缘膜的可靠性。

10. 发明专利

JP2013232556A Silicon carbide semiconductor element manufacturing method 有权
标题翻译：硅碳化硅半导体元件制造方法
公开(公告)号：JP2013232556A
公开(公告)日：2013-11-14
申请号：JP2012104223
申请日：2012-04-27
申请人： National Institute Of Advanced Industrial & Technology , 独立行政法人産業技術総合研究所 , Fuji Electric Co Ltd , 富士電機株式会社
发明人： FUKUDA KENJI , IWAMURO NORIYUKI , GOTO MASAHIDE
IPC分类号： H01L21/28
摘要： PROBLEM TO BE SOLVED: To achieve low ohmic resistance of a rear face to reduce erosion of an outermost surface due to sacrificial oxidation and the like; enable reduction in energy and time which are necessary for ion implantation; and inhibit increase in size of an ion implantation device provided in a production line.SOLUTION: A silicon carbide semiconductor element manufacturing method in which an Si face 1a is set as a surface and a C-face 1b is set as a rear face, comprises: performing ion implantation of an n-type dopant from the C-face 1b of the silicon carbide substrate 1; and performing ion implantation of a p-type dopant to a region of the silicon carbide substrate 1, which is shallower than a region of the n-type dopant on the rear face. By doing this, erosion of an outermost surface due to sacrificial oxidation and the like can be reduced.
摘要翻译：要解决的问题：为了实现背面的低欧姆电阻，以减少由于牺牲氧化等引起的最外表面的侵蚀; 能够减少离子注入所需的能量和时间; 并且抑制在生产线中提供的离子注入装置的尺寸增加。解决方案：将Si面1a设置为表面并将C面1b设置为背面的碳化硅半导体元件制造方法包括：从碳化硅衬底1的C面1b进行n型掺杂剂的离子注入; 并且对碳化硅衬底1的比背面上的n型掺杂剂的区域浅的区域进行p型掺杂剂的离子注入。通过这样做，可以减少由于牺牲氧化等导致的最外表面的侵蚀。

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