专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPS637700A MECHANISM FOR LOADING AND UNLOADING OF SUBSTRATE 失效
公开(公告)号：JPS637700A
公开(公告)日：1988-01-13
申请号：JP14970486
申请日：1986-06-27
申请人： FUJITSU LTD , TOYO GIKEN KOGYO KK
发明人： AMADA TOYOMITSU , ABE TOSHIO , OGAWA HITOSHI , USUDA HITOSHI , OMORI MASAO
IPC分类号： B65G47/90 , B65G1/04 , B65G1/06 , B65G1/07 , B65G47/57 , B65G47/96 , B65G49/00 , H05K3/34 , H05K13/02

2. 发明专利

JPH01272797A APPARATUS FOR LOADING BASE PLATE TO PLATING JIG FITTED WITH FRAME 失效
公开(公告)号：JPH01272797A
公开(公告)日：1989-10-31
申请号：JP9932788
申请日：1988-04-23
申请人： FUJITSU LTD , TOYO GIKEN KOGYO KK
发明人： AMADA TOYOMITSU , OGAWA HITOSHI , KIKUCHI MINORU , MIMURA KENJI
IPC分类号： B65H29/10 , B65H29/44 , C25D17/06 , C25D17/08
摘要： PURPOSE:To automatically load a base plate with a simple mechanism by enabling a stopper supporting the lower end of a base plate to be taken out and introduced for the base plate supporting face of a reversing table in a process wherein the base plate is contrarotated with the reversing table and provided to an auxiliary electrode frame. CONSTITUTION:A base plate 1 is placed on the base plate supporting face 2a of a reversing table 2 in a horizontal state and the stopper 3 fitted to the table 2 is projected on the face 2a with a cylinder 4 and the lower end of the base plate 1 is allowed to abut thereon. In this state, the table 2 is rotated at about 90 deg. with a cylinder 5 around an axis 6a in the direction A and the base plate 1 is regulated to a vertical state and made adjacent to the inside of an auxiliary electrode frame 20 in the case of plating and the lower end of the base plate is fitted to plural groove members 24 on the lower frame part 23 of the frame 20 and the base plate is set to a jig. In this case, the base plate 1 is supported with a back receiving bracket 9 which is progressed in the direction B and furthermore the upper end of the base plate 1 is clamped with a mechanism 10. When the table 2 is returned to the original position, the stopper 3 is pulled to the inside of the face 2a. Thereby the stopper 3 does not interface with the base plate 1 and the frame 20, etc.

3. 发明专利

JPH06211328A CONVEYER DEVICE FOR DOUBLE-COATED PRINTED WIRING BOARD 失效
公开(公告)号：JPH06211328A
公开(公告)日：1994-08-02
申请号：JP18533992
申请日：1992-07-13
申请人： FUJITSU LTD , ALMEX INC
发明人： KAWANA EISHIROU , AMADA TOYOMITSU , NAKAYAMA AKITAKA , ABE MICHIHARU , OGAWA HITOSHI , MIMURA KENJI , SHINOHARA NOBUAKI
IPC分类号： B65G13/02 , B65G39/12
摘要： PURPOSE:To provide a conveyer device whereby a printed wiring board can be conveyed without coming into contact with a liquid-state object applied to both sides of the printed wiring board. CONSTITUTION:In a conveyer device suited for conveying a printed wiring board 12 of applying a liquid-state object to its both sides, the device is constituted by separating the first/second drive roller rows 16, 18, constituted of a plurality of drive rollers 14, from each other by a predetermined distance and also by setting up these first/second drive roller rows 16, 18 tilted in almost V-shape so that sides opposed to each other of the first/second drive roller rows 16, 18 are arranged near.

4. 发明专利

JPH05226809A ETCHING METHOD FOR PRINTED WIRING BOARD 失效
公开(公告)号：JPH05226809A
公开(公告)日：1993-09-03
申请号：JP3051892
申请日：1992-02-18
申请人： FUJITSU LTD
发明人： MATSUMOTO TAKESHI , TAKAHASHI YOSHITAKE , OGAWA HITOSHI , YUZAWA HIROKAZU
IPC分类号： C23F1/00 , C23F1/02 , C23F1/08 , H05K3/06
摘要： PURPOSE:To facilitate clearer patterning which has little width unevenness and has a uniform shape in order to form various patterns from a low density pattern to a high density pattern. CONSTITUTION:Etchant is sprayed against the one side of a board 12 to etch mainly the one side conductor of the board 12 while the board 12 is conveyed horizontally or vertically. In order to prevent the penetration of the etchant into the other side of the board 12, it is recommended to make air blow against the other side of the board.

5. 发明专利

JPH0548248A PRINTED CIRCUIT BOARD CLEANING APPARATUS 失效
公开(公告)号：JPH0548248A
公开(公告)日：1993-02-26
申请号：JP19959491
申请日：1991-08-08
申请人： FUJITSU LTD
发明人： KAWANA EISHIROU , OGAWA HITOSHI
IPC分类号： B08B3/12 , H05K3/26
摘要： PURPOSE:To provide a printed circuit board cleaning apparatus which can sufficiently clean inside of small-diameter through holes. CONSTITUTION:A printed circuit board 6 to be cleaned is considered as a wall of one surface of a sealing chamber, and a cleaning chamber 3 is sealed by a box 2 and the board 6. Pressurized cleanser is supplied into the sealed chamber 3 by a pressure pump 14, and cleanser is forcibly passed via the through holes of the board 6. The air collected in the through holes 7 is forcibly discharged by the pressurized cleanser, and the inner walls of the holes 7 can be effectively cleaned. When an ultrasonic vibration is applied to the cleanser by ultrasonic vibrators 16, 16', its cleaning effect can be enhanced.

6. 发明专利

JPH04235038A APPARATUS FOR PULLING OUT REFERENCE PIN FOR LAMINATION 失效
公开(公告)号：JPH04235038A
公开(公告)日：1992-08-24
申请号：JP1247491
申请日：1991-01-10
申请人： FUJITSU LTD
发明人： KAWANA EISHIROU , OGAWA HITOSHI
IPC分类号： B29C43/20 , B29C43/32 , B29K105/06 , B29L31/34 , B32B37/10 , H05K3/46
摘要： PURPOSE:To provide the title apparatus enhanced in workability and general-purpose properties capable of pulling out a reference pin without damaging a laminating jig. CONSTITUTION:In an apparatus pulling out at least two reference pins 13 from a laminated substrate 40 aligned by the insertion of the reference pins 13, a feed means 10 feeding the laminated substrate and a stopper means 14 stopping the laminated substrate 40 fed by the feed means 10 at a predetermined position are provided. Further, punch units 22 each having a push-out punch 44 pushing out the reference pins 13, the die 66 having the hole 66a in which the push-out punch 44 is inserted, the drive means 50 driving the push-out punch and a substrate arranging means 42 centering the laminated substrate 40 with respect to the direction crossing the feed direction at a right angle are arranged on both sides of the feed direction of the laminated substrate 40 at least one by one.

7. 发明专利

JPH04154312A OPERATIONAL AMPLIFYING CIRCUIT 失效
公开(公告)号：JPH04154312A
公开(公告)日：1992-05-27
申请号：JP27982690
申请日：1990-10-18
申请人： FUJITSU LTD , FUJITSU VLSI LTD
发明人： OGAWA HITOSHI , MITSUSAKI HIROYUKI
IPC分类号： H03F3/45
摘要： PURPOSE:To drive various loads without consuming unnecessary electric power by selecting and outputting a bias voltage corresponding to the load from in plural bias voltages which can be set by a variable bias circuit. CONSTITUTION:When digital binary signals D1-D4 of 4 bits are inputted, its binary signals D1-D4 are converted to an analog voltage by a resistance string 5, and its analog voltage is amplified by a differential circuit 1 and an output stage 3 and outputted as an output signal Vout to a load circuit 4. In this case, for instance, when resistance values of each resistance R3, R4 and R5 of a variable bias circuit 6 are set such as R3>R4>R5, a bias voltage supplied to transistors TR5, TR7 in the case each resistance R3, R4 and R5 is connected to a drain of a transistor TR9 becomes three stages in order of R3

8. 发明专利

JPH0232618A BUFFER CIRCUIT 失效
公开(公告)号：JPH0232618A
公开(公告)日：1990-02-02
申请号：JP18289988
申请日：1988-07-22
申请人： FUJITSU LTD , FUJITSU VLSI LTD
发明人： OGAWA HITOSHI , INAGAKI YASUKUNI
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8238 , H01L27/092 , H03K17/16 , H03K19/0175 , H03K19/0185 , H03K19/0948
摘要： PURPOSE:To prevent the malfunction of an integrated circuit from being generated by suppressing the current flow of a through current at a low level by providing a voltage drop device between a first MOS transistor and a first power source, and a third MOS transistor of n-channel between a second power source whose voltage level is less than that of the first power source and a second MOS transistor. CONSTITUTION:When both the first and second MOS transistors P1 and N1 are energized at the time of switching, the through current flows on the voltage drop device R1, and an impression voltage on the gate of the third MOS transistor N2 drops, then, the third transistor N2 is de-energized, which cuts off the through current. In a stationary state, no through current flows, therefore, the third transistor N2 is energized. Therefore, the current flow of the through current is reduced, and a noise level on a ground line is lowered. In such a way, it is possible to prevent the malfunction of the integrated circuit from being generated.

9. 发明专利

JP2009065702A Data processing method 有权
标题翻译：数据处理方法
公开(公告)号：JP2009065702A
公开(公告)日：2009-03-26
申请号：JP2008286113
申请日：2008-11-07
申请人： Fujitsu Ltd , 富士通株式会社
发明人： OGAWA HITOSHI , MAKABE HIDEO
IPC分类号： H04L12/28 , G06F13/38
摘要： PROBLEM TO BE SOLVED: To provide a data processing method and apparatus capable of guaranteeing playback of a motion picture or the like with reality by ensuring continuous transfer and real-time transfer. SOLUTION: In one Isoc cycle, an Isoc packet 31 for reception read from a first storage memory storing an Isoc packet transferred in an Isoc transfer mode is transferred to an internal device, an Isoc packet 31 for transmission from the internal device is stored in the first storage memory, and the Isoc packet 31 for transmission is transferred to external equipment in the Isoc transfer mode. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够通过确保连续传送和实时传送而实际地保证电影播放等的数据处理方法和装置。解决方案：在一个Isoc循环中，从存储以Isoc传送模式传送的Isoc包的第一存储存储器读取的用于接收的Isoc包31被传送到内部装置，用于从内部装置发送的Isoc包31 存储在第一存储器中，并且用于传输的Isoc包31以Isoc传送模式被传送到外部设备。版权所有（C）2009，JPO＆INPIT

10. 发明专利

JP2005339512A Data processing method and data processor 有权
标题翻译：数据处理方法和数据处理器
公开(公告)号：JP2005339512A
公开(公告)日：2005-12-08
申请号：JP2005068786
申请日：2005-03-11
申请人： Fujitsu Ltd , Fujitsu Vlsi Ltd , 富士通ヴィエルエスアイ株式会社 , 富士通株式会社
发明人： OGAWA HITOSHI , MAKABE HIDEO
IPC分类号： G06F13/28 , G06F13/38 , H04L12/28 , H04L12/40
摘要： PROBLEM TO BE SOLVED: To provide a data processing method and a data processor by which continuous transfer and real time transfer are secured and reproduction of a moving image, etc. with reality is assured. SOLUTION: A FIFO 38a for Isoc transfer which stores an Isoc packet in an Isoc transfer mode and a FIFO 30b for Asyn transfer which stores an Asyn packet of in an Asyn transfer mode are separately provided, respectively. In addition, a first DMA I/F 39a which inputs/outputs the Isoc packet in the Isoc transfer mode and a second DMA I/F 39b which inputs/outputs the Asyn packet in the Asyn transfer mode are separately provided, respectively. Then, the Isoc packet to be transferred in the Isoc transfer mode and the Asyn packet to be transferred in the Asyn transfer mode are stored in separate FIFOs 38a, 38b, respectively and inputted/outputted to separate DMA I/Fs 39a, 39b, respectively. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种数据处理方法和数据处理器，通过该数据处理方法和数据处理器确保连续传送和实时传送，并且确保具有现实的运动图像等的再现。解决方案：分别提供存储Isoc传输模式中的Isoc数据包的FIFO 38a和存储Asyn传输模式的Asyn数据包的Asyn传输的FIFO 30b。此外，分别提供在Isoc传送模式中输入/输出Isoc数据包的第一DMA I / F 39a和在Asyn传送模式下输入/输出Asyn数据包的第二DMA I / F 39b。然后，将以Isoc传送模式传送的Isoc数据包和Asyn传输模式下传输的Asyn数据包分别存储在单独的FIFO 38a，38b中，并分别输入/输出到分开的DMA I / F 39a，39b 。版权所有（C）2006，JPO＆NCIPI

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式