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1. 发明专利

JPS64850A CONTINUITY TEST LINE SETTING SYSTEM 失效
公开(公告)号：JPS64850A
公开(公告)日：1989-01-05
申请号：JP15598587
申请日：1987-06-23
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： HIDAKA TOSHIO , KOGURE KOJI
IPC分类号： H04M3/26 , H04J3/14 , H04Q1/24
摘要： PURPOSE:To detect trouble which occurs in a double buffer type time division switch, by setting a time slot for pilot signal extract ion as prescribed. CONSTITUTION:An address generating means 600 sets the write time and the read time of data memories 100 and 200 so that the time of a time slot TSr where a pilot signal P is extracted from a double buffer type time division switch 300 is equal to or behind the time of a time slot TSw where the signal P is stored in the switch 300. Thus, in case of a frame under which one data memory is operated in the same manner as single buffer type because of the occurrence of trouble in the switch 300, the signal P stored in the time slot TSw is extracted in the time slot TSr in the same frame F, and the inter-frame continuity between this signal extraction and extraction of the signal P which is stored in the time slot TSw in the just preceding frame F in the other data memory cannot be held. Thus, trouble of the double buffer type time division switch 300 is detected as the result of continuity test.

2. 发明专利

JPH0574279B2 失效
公开(公告)号：JPH0574279B2
公开(公告)日：1993-10-18
申请号：JP10534783
申请日：1983-06-13
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD
发明人： MURAKAMI KOZO , KOGURE KOJI , YAMAOKA KENTARO , TAKEUCHI WATARU , HORIKI AKIRA
IPC分类号： H04Q11/04

3. 发明专利

JPS61224629A FRAME SYNCHRONISM DEVICE IN TIME DIVISION LINE CONCENTRATOR 失效
公开(公告)号：JPS61224629A
公开(公告)日：1986-10-06
申请号：JP6361385
申请日：1985-03-29
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NEC CORP , FUJITSU LTD
发明人： MORI MAKOTO , KOGURE KOJI , FUJITSUKA ISAMU , MURATA KOICHI , KIYONO NAOHISA
IPC分类号： H04J3/06 , H04L7/08 , H04Q11/04
摘要： PURPOSE:To allow a controlling and supervising circuit side to synchronize concentratingly and efficiently a multi-frame from a subscriber circuit by setting a frame identification flat at each multi-frame from the subscriber circuit and allowing the controlling and supervising circuit side to identify the frame identification flag so as to apply frame synchronization. CONSTITUTION:The subscriber circuits SLC1-SLCN have respectively a multi- frame generating function and a function receiving the multi-frame via a BHW and applying frame synchronization. The frame synchronization is executed by identifying a frame identification flag added with control information SD. In generating the multi-frame by the subscriber circuits SLC1-SLCN, the frame identification flag is added to state information SCN. The state information SCN added with the said flag is sent via an FHW. The controlling and supervising circuit SDC has a function receiving the multi-frame via the FHW and applying frame synchronization and a multi-frame generating function adding a frame identification flag to the control information SD and sending the result to the BHW. The frame synchronization is executed by identifying the frame identification flag in the multi-frame via the FHW.

4. 发明专利

JPS6234436A DATA TROUBLE DETECTING CIRCUIT 失效
公开(公告)号：JPS6234436A
公开(公告)日：1987-02-14
申请号：JP17344385
申请日：1985-08-06
申请人： NEC CORP , NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD
发明人： ONO CHUKICHI , KOGURE KOJI , KURODA KIYOHIKO
IPC分类号： H04L1/00
摘要： PURPOSE:To reduce the quantity of the hardware used in a data trouble detecting circuit so as to make maintenance of the circuit easier, by making the selecting designation of a selector the same as parity rule designating information. CONSTITUTION:Usually, command from a parity rule designating information line 70 is an odd parity rule and a 2-1 selector 9 selects an OR circuit 8a. If a trouble occurs on at least one side of memory circuits 41 and 42 under this condition, the output of the OR circuit 8a becomes to have a logic '1' and trouble information is outputted to the check result outputting information line 60 of the 2-1 selector 9. When the information from the information line 70 is changed to an even parity rule, the selector 9 selects an AND circuit 8b. The output of the AND circuit 8b becomes to have a logic '1' only when the trouble information is outputted to both check result outputting information lines 61 and 62 and trouble information indicating that normality of parity generating circuits 21 and 22 and parity checking circuits 51 and 52 is confirmed is outputted to the check result outputting information line 60 of the 2-1 selector 9.

5. 发明专利

JPH01151860A SUBRATE SWITCHING CIRCUIT 失效
公开(公告)号：JPH01151860A
公开(公告)日：1989-06-14
申请号：JP30947787
申请日：1987-12-09
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： FUJITSUKA ISAMU , KOGURE KOJI
IPC分类号： H04L12/20 , H04L12/50
摘要： PURPOSE:To communicate the information of a desired subrate effectively by distributing bits of input information including the subrate information so as to use only the desired subrate information as the information based on control information representing the type of bit distribution. CONSTITUTION:A bit distribution means 3 receiving input information for each time slot including the subrate information from an incoming line concentration switch 1 distributes bits and gives an output so as to use the input information as the information by the subrate information based on the kind represented by control information from a storage means 2. In this case, let the control information of the time slot set in the storage means 2 be a kind representing bit distribution of input bits in 4-bits at 32kb/s into output bits of 2 -2 and 2 -2 , then the distribution means 3 applies substrate switching to apply bit distribution of 4-bit in 32kb/s into 2 -2 and 2 -2 . Thus, the subrate information is communicated effectively.

6. 发明专利

JPS6243300A CHANNEL LINE CONCENTRATOR 失效
公开(公告)号：JPS6243300A
公开(公告)日：1987-02-25
申请号：JP18333885
申请日：1985-08-20
申请人： NEC CORP , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKEUCHI WATARU , YOKOI NOBUTAKA , KOGURE KOJI
IPC分类号： H04Q11/04
摘要： PURPOSE:To use effectively time division multiplex highways by allowing time division multiplex up highways and time division multiplex down highways to exist together on time division multiplex junctor highways. CONSTITUTION:Time division multiplex up highways 16 and 17 and a time division multiplex down highway 21 of outputs of the first channel memories 1, 3, and 6 are stored in a select switch 35. Information which is used to select one of highways of outputs of the first channel memories 1, 3, and 6 is written in a select switch control memory 13, and this information is outputted from a control line 28 to select one of highways of outputs of the first channel memories by the select switch 35. Outputs of the second channel memories 2 and 4 are time division multiplex down highways 19 and 20, and the output of the second channel memory 5 is a time division multiplex up highway 18.

7. 发明专利

JPH06311227A SWITCHING DEVICE FOR N+1 REDUNDANT CONFIGURATION 失效
公开(公告)号：JPH06311227A
公开(公告)日：1994-11-04
申请号：JP9757493
申请日：1993-04-23
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： KATAOKA HIDEKI , KOGURE KOJI
IPC分类号： H04B1/74 , H04M3/22 , H04Q3/545
摘要： PURPOSE:To improve cost effectiveness possibility and reliability. CONSTITUTION:L pieces of devices A100-A131 are respectively connected to devices B400-B421 by a switching device SE and M pairs of duplex links. One spare is provided corresponding to N pieces of devices B, and the switching device is made into so-called N+1 redundant configuration. Corresponding to an integer K larger than '2' and smaller than LXM, 2K pieces of changeover switches 502, 502', 512 and 512' provided with LXMXNdivided by K pieces of terminals on the device A side and LXMX(N+1)divided by K pieces of terminals on the device B side are prepared and installed while being divided into J pieces of first and second switching devices (J=2 in this case) (one device for 500 and 501 and the other one device for 510 and 511) more than 2 and less than 2K, and the link of a '0' system which first digit is '0' in one pair of duplex link to connect the devices A and B and the link of a '1' system, which first digit is '1' are respectively housed in the different first and second switching devices.

8. 发明专利

JPH05244674A 失效
公开(公告)号：JPH05244674A
公开(公告)日：1993-09-21
申请号：JP3967992
申请日：1992-02-26
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： ONISHI KOICHI , YASUDA SHINJI , KOGURE KOJI , SUZUKI SHIGEHIKO
IPC分类号： H04Q11/04 , H04L12/24 , H04L12/26
摘要： PURPOSE:To prevent connection data from being given to an inter-exchange module connection mechanism so as to improve reliability, to dissolve the complication of an operation and to solve the problem of a duplex processing in a call path setting system between exchange modules in a building block-tape- exchange. CONSTITUTION:An exchange module l becoming a path setting request source transmits a path setting request message to a path connection destination exchange module 21, and it judges the propriety of setting. When it is possible, information required for the setting of a path is transmitted to the inter- exchange module connection mechanism 6.

9. 发明专利

JPS62104254A FAULT DIAGNOSTIC SYSTEM 失效
公开(公告)号：JPS62104254A
公开(公告)日：1987-05-14
申请号：JP24268785
申请日：1985-10-31
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： SHIMAZAKI HITOSHI , AKIYAMA NOBUYOSHI , KOGURE KOJI
IPC分类号： H04M3/26 , H04Q1/24
摘要： PURPOSE:To reduce a fault diagnostic time by selecting one of plural operating sections at fault occurrence, changing it into a block section, switching an incoming line of the block section from an outgoing line of the operating system into a corresponding outgoing line of a spare system by means of a selector to apply fault diagnosis of the block section sequentially thereby applying the same fault diagnostic method as a duplicated equipment to a simplex equipment. CONSTITUTION:If a fault takes place in the simplex equipment 3, a controller 4 changes the operating section 3-4 of the simplex equipment as the block section and disconnects the operating section from the operating system 1-1 and connect it to the spare system 1-2, the spare system 1-2 and the simplex equipment block section 3-4 receive a control order to constitute the test bus in a route of pattern generator 5-1 terminal 7-2 spare system 1-2 terminal 8-24 selector 2-4 terminal 9-4 block section 3-4 terminal 10-4 pattern checker 5-2. As the result of test, when no fault exists in the simplex equipment operation section 3-4, other operation sections 3-3-3-1 of the simplex equipment are diagnosed sequentially by the same method.

10. 发明专利

JP2505441B2 失效
公开(公告)号：JP2505441B2
公开(公告)日：1996-06-12
申请号：JP1852987
申请日：1987-01-30
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： KAWAMURA NORYUKI , KOGURE KOJI
IPC分类号： H04M3/00 , H04M3/60 , H04M7/00

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