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1. 发明专利

JPS60134943A SCAN-OUT SYSTEM 失效
公开(公告)号：JPS60134943A
公开(公告)日：1985-07-18
申请号：JP24340683
申请日：1983-12-23
申请人： FUJITSU LTD
发明人： SUGIZAKI HARUO
IPC分类号： G06F11/22 , G06F11/267
摘要： PURPOSE:To improve the throughout of a program by providing a data control register in accordance with a data register and suppressing and setting an optional byte of th data control register to ''0'' by a program of a service processor. CONSTITUTION:First, the service processor (SVP) program sets 0 suppression of an optional byte to a data control register 32, and hereafter, indicated bytes of all data are suppressed to 0. Consequently, a complicated program which indicates comparison after 0 clear due to the progam processing of the SVP is unnecessary even if bytes which do not exist on hardware are undefined data or data is other than ''0'' fixedly. When a large quantity of data in a memory or the like having the same data format is processed, the number of dynamic steps of the program is reduced.

2. 发明专利

JPS6086631A SCAN-IN SYSTEM 失效
公开(公告)号：JPS6086631A
公开(公告)日：1985-05-16
申请号：JP19480583
申请日：1983-10-18
申请人： FUJITSU LTD
发明人： SUGIZAKI HARUO
IPC分类号： G06F11/22 , G01R31/3185 , G06F11/10
摘要： PURPOSE:To execute scan-in of 1-byte units by adding a parity mode designating circuit and providing bits for designating a parity generate or forced mode in 1-byte unit. CONSTITUTION:Parity generated by a program of a service processor SVP1 is scanned in from, for example, a 4-byte register of memory 21 of a device 2 as a control object in byte units. In this case, a parity value is set to the first optional 4 bits of 1-byte data written from the processor SVP1 to a parity register 13. Bits which designate the parity generate mode or the parity forced mode are assigned to 4 left bits. Thus, logical ''1'' is set only in the parity forced mode and logical ''0'' is set in the other modes in accordance with bytes to execute scan-in of 1-byte units.

3. 发明专利

JPS5491157A AUTOMATIC SWITCHING SYSTEM OF CONTROL WORD TYPE 失效
公开(公告)号：JPS5491157A
公开(公告)日：1979-07-19
申请号：JP15906577
申请日：1977-12-28
申请人： FUJITSU LTD
发明人： SUZUKI YOUICHI , KUGIMIYA NORIO , HANADA AKIO , NAKAMURA HIROSHI , SUGIZAKI HARUO
IPC分类号： G06F13/12 , G06F9/06 , G06F9/32 , G06F13/00 , H04L29/10
摘要： PURPOSE:To make it possible to read the control word of data width specified by a program automatically from a memory by providing the instruction of the address type indication. CONSTITUTION:When the read signal is supplied to memory 4, contents of register 10 are supplied to memory 4 through address register 11, and the associated control word is read. The read control word is inputted to control word reguest determination circuit 8. The instruction of the address type indication is previously set to type memory register 7; and, for example, if contents of type memory register 7 indicates that the control word is 2-word type, control word request determination circuit 8 increments contents of address register 11 by one addrss adder 9, and data is read again from the memory based on the incremented address and is sent to control word request determination circuit 8, and gate G is closed.

4. 发明专利

JPS5311548A ERROR INFORMATION TRANSFER CONTROL SYSTEM 失效
公开(公告)号：JPS5311548A
公开(公告)日：1978-02-02
申请号：JP8584976
申请日：1976-07-19
申请人： FUJITSU LTD
发明人： SAWADA TAKETOYO , MITA TERUYOSHI , SUGIZAKI HARUO , SEKIKAWA FUMIO , SATOU MASAO
IPC分类号： G06F11/30 , G06F11/00
摘要： PURPOSE:To achieve an error information transfer at the memory access time given from a memory using unit without having a special transfer time and without providing a signal line for each of various error signals.

5. 发明专利

JPS53947A 1 BIT ERROR CORRECTION CIRCUIT BY HAMMING CODE 失效
公开(公告)号：JPS53947A
公开(公告)日：1978-01-07
申请号：JP7525076
申请日：1976-06-25
申请人： FUJITSU LTD
发明人： SUZUKI YOUICHI , MITA TERUYOSHI , SUGIZAKI HARUO , SATOU MASAO , HIWATARI AKITO
IPC分类号： G06F12/16 , G06F11/10 , H03K19/00 , H03K19/003
摘要： PURPOSE:To prevent a delay in memory access time where no error is present in a circuit having 1-bit correction function by a hamming code by constituting a sense register with a J - K FF.

6. 发明专利

JPH02202244A INFORMATION TRANSFER SYSTEM 失效
公开(公告)号：JPH02202244A
公开(公告)日：1990-08-10
申请号：JP2129889
申请日：1989-01-31
申请人： FUJITSU LTD
发明人： SUGIZAKI HARUO
IPC分类号： G06F11/30 , G06F13/00 , H04L7/00 , H04L29/02
摘要： PURPOSE:To transfer internal information to a host line adaptor control section (LAC) without increasing exclusive hardware by generating a maintenance use synchronizing character code (MSYN) and adding the code to internal information such as internal state information or log information. CONSTITUTION:A character code different from the substantial synchronizing establishing character code (SYN) such as X'20' is decided as the maintenance use synchronizing character code (MSYN) between a line adaptor (LA) 1 and a line adaptor control section (LAC). When no transfer data exists and there is a request to transfer the internal information in the line adaptor (LA) 1 to the host line adaptor control section (LAC), the maintenance use synchronizing character code (MSYN) is generated and added to the head of the internal information and the internal information of the line adaptor (LA) 1 is transferred to the line adaptor control section (LAC). When the maintenance use synchronizing character code (MSYN) is received in the host line adaptor control section (LAC), the LAC acts like processing the succeeding data as the internal information in the line adaptor (LA) 1.

7. 发明专利

JPS61188644A LOG-OUT SYSTEM 失效
公开(公告)号：JPS61188644A
公开(公告)日：1986-08-22
申请号：JP2781185
申请日：1985-02-15
申请人： FUJITSU LTD
发明人： SUGIZAKI HARUO
IPC分类号： G06F11/34
摘要： PURPOSE:To elevate a utilization efficiency of an auxiliary memory device medium by using a area for extension log-out as a basic log-out area according to necessity. CONSTITUTION:A flag 15 displays whether the extension log-out area corresponding to the extension logging index to which belongs the flag may be used as the basic log-out area. When informed that the basic log-out area 3a is full, a service processor executing the basic log-out checks the flag 15 for indices 11a-12a for the extension log-out. When the flag 1, that is, when the corresponding extension log-out area can be used as the basic log-out area, the corresponding index is produced and the log-out data are stored in the prescribed extension log-out area.

8. 发明专利

JPH03189823A INSTRUCTION EXECUTING SYSTEM 失效
公开(公告)号：JPH03189823A
公开(公告)日：1991-08-19
申请号：JP33023089
申请日：1989-12-20
申请人： FUJITSU LTD
发明人： SUGIZAKI HARUO
IPC分类号： G06F9/30
摘要： PURPOSE:To delay the processing time of a program to an arbitrary time by setting an object program instruction address for delaying the processing time and the time for delaying it. CONSTITUTION:The system is provided with an address setting part 1 for setting an address Tc of a program instruction for delaying a processing time, a delay time setting part 4 for setting a delay time value Tc of the program instruction, an address comparing part 3, a counter 7 and a delay time comparing part 5. In such a state, when an execution address of the program instruction coincides with a set value of the address setting part 1, the execution of the program instruction is inhibited, and when a counted value of the counter 7 coincides with a set value of a delay time setting part 4, the execution of the program instruction is restarted. In such a manner, by only setting a program instruction address (Ac) for delaying the processing time and the time value (Tc), the processing time of the program is delayed to an arbitrary time.

9. 发明专利

JPS6051348A LINE TRACING SYSTEM 失效
公开(公告)号：JPS6051348A
公开(公告)日：1985-03-22
申请号：JP15953883
申请日：1983-08-31
申请人： FUJITSU LTD
发明人： SUGIZAKI HARUO
IPC分类号： H04L29/14 , G06F13/00 , H04L13/00
摘要： PURPOSE:To obtain detailed trace information by providing line trace indication bits in line control words of a communication controller, and wirting line control words successively in a memory for tracing if indication bits are set in line scanning. CONSTITUTION:When line trace is required by a control program, the line tracing operation of trouble analysis in a line control part 16 sets the address of a line to be traced to a control program indication address register 9 by an output instruction and sets a trace indication bit 15 in a line control word in a line control memory 14. Contents of a scanning address register 8 in the control part 16 are counted up successively, and contents of a corresponding line control word are set to a read register 10; and if the indication bit 15 is set, contents of the line control word are written in a memory 18 for tracing and an address register 17 for tracing is counted up by +1, and the control program resets the indication bit 15 to stop tracing in case of trouble detection or the like, and contents of the memory 18 are outputted as required after reading.

10. 发明专利

JPS59119944A CIRCUIT CONTROL DIAGNOSIS SYSTEM 失效
公开(公告)号：JPS59119944A
公开(公告)日：1984-07-11
申请号：JP22842382
申请日：1982-12-27
申请人： FUJITSU LTD
发明人： SUGIZAKI HARUO
IPC分类号： H04L29/14 , H04L13/00
摘要： PURPOSE:To perform a test for the confirmation of a modulating/demodulating device by fetching a pseudo signal of the modulating/demodulating device when the coincidence of address is obtained between a diagnosis subjected circuit and a scanning circuit and also the address of the diagnosis subjected circuit is effective. CONSTITUTION:An effective bit is set to a diagnosis address register 1 to show that the address of a diagnosis subjected circuit is effective. While an ON or OFF state is set to a pseudo signal register 2 for the bit corresponding to each state signal in order to simulate the state signal of a modulating/demodulating device. Then the address of a scanning circuit is compared with the contents of the register 1 by a comparator 3, and the comparator 3 delivers a coincidence signal. At the same time, the effective bit of an effective bit holding part is turned on. Under such conditions, the contents of the register 2 are delivered.

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