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1. 发明专利

JPS617663B2 JPS617663B2 - 失效
公开(公告)号：JPS617663B2
公开(公告)日：1986-03-07
申请号：JP15309580
申请日：1980-10-31
申请人： Fujitsu Ltd
发明人： OOYAMA TOMONAGA , SATO SHINICHI
IPC分类号： G06F13/14 , G06F11/00 , G06F13/00 , G06F13/40
CPC分类号： G06F13/4022

2. 发明专利

JPS5282040A DATA PROCESSING UNIT RESET CONTROL 失效
公开(公告)号：JPS5282040A
公开(公告)日：1977-07-08
申请号：JP15637575
申请日：1975-12-29
申请人： FUJITSU LTD
发明人： KAMATA MASAYOSHI , OOYAMA TOMONAGA
IPC分类号： G06F9/22 , G06F9/06 , G06F9/34
摘要： PURPOSE:To use control program memory more effectively by enabling every needed register to be concurrently reset by 1 micro instruction.

3. 发明专利

JPH0451854B2 失效
公开(公告)号：JPH0451854B2
公开(公告)日：1992-08-20
申请号：JP3797385
申请日：1985-02-27
申请人： FUJITSU LTD
发明人： OOYAMA TOMONAGA
IPC分类号： G06F3/06 , G06F9/445 , G06F13/00

4. 发明专利

JPS6146541A Data write system 失效
标题翻译：数据写入系统
公开(公告)号：JPS6146541A
公开(公告)日：1986-03-06
申请号：JP16727284
申请日：1984-08-11
申请人： Fujitsu Ltd
发明人： KURIHARA YASUO , MATOBA TATSUO , FUKAZAWA FUMIO , KAWAMOTO MASAKAZU , OOYAMA TOMONAGA
IPC分类号： G06F11/10 , G06F13/00
摘要： PURPOSE: To easily perform error detection by generating a check code by an input/output controller and leaving the check code corresponding to old data in a memory even if data transfer in process is interrupted.
CONSTITUTION: An input/output device 3 reads the memory 35, check bits are checked, and read data are transferred to the input/output controller 2. The device 2 inputs data of every M units of the sent data 27 and a check code of every N units to a check code inspecting circuit 24 and a data inspecting circuit 29 checks error detection code data left in the circuit 24 when a read of (M+N)- unit data is finished. When the data have a specific pattern, it is decided that there is no error. Data 21 of subsequent M units and a check bit 22 checked by a check circuit 26 are transferred to a channel 1 and a check bit 12 is checked by a check circuit 14.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过输入/输出控制器生成检查代码，即使在数据传输过程中断时，仍将与旧数据对应的校验码留在存储器中，便于进行错误检测。构成：输入/输出装置3读取存储器35，检查位被检查，读取的数据被传送到输入/输出控制器2.装置2输入发送数据27的每个M个单元的数据和一个检查码检查代码检查电路24的每N个单元和数据检查电路29检查（M + N） - 单位数据的读取结束时在电路24中剩余的错误检测码数据。当数据具有特定的模式时，决定没有错误。后续M单元的数据21和由检查电路26检查的校验位22被传送到通道1，并且校验位12由校验电路14检查。

5. 发明专利

JPS5965333A Input and output control system 失效
标题翻译：输入和输出控制系统
公开(公告)号：JPS5965333A
公开(公告)日：1984-04-13
申请号：JP17563282
申请日：1982-10-06
申请人： Fujitsu Ltd
发明人： OOYAMA TOMONAGA
IPC分类号： G06F13/14 , G06F13/36
CPC分类号： G06F13/36 , G06F13/14
摘要： PURPOSE:To ensure the impartial service to both input and output requests despite of difference in processing speed of a high-order device, by providing such as a means which suppresses temporarily the input and output requests given from the high-order device and has the priority on these requests. CONSTITUTION:A means is provided to suppress temporarily the input and output requests given from a high-order device and has the priority on its requests. For instance, the signal which is produced when the input/output processing is finished by a channel at the other side is supplied to an OR gate 1 together with the signal which is produced when the channel of the other side gives a report of a busy state to an upper device while the own channel selects an input/ output device for an input/output operation. Then a register 3 is set with the signals supplied to the gate 1, and the register 3 transmits a signal showing that the input/output device is under use to a timer 4. The signal is supplied to an OR gate 2 after a prescribed period of time counted by the timer 4. Then the register 3 is reset by the output of the gate 2.
摘要翻译：目的：为了确保对高阶设备的处理速度差异，对输入和输出请求的公正服务，通过提供诸如暂时抑制来自高阶设备的输入和输出请求的装置，并且具有优先考虑这些请求。构成：提供了一种手段来暂时抑制从高阶装置给出的输入和输出请求，并且对其请求具有优先权。例如，当通过另一侧的信道完成输入/输出处理时产生的信号与在另一侧的信道给出忙碌的报告时产生的信号一起被提供给或门1 状态到上部设备，而自己的通道选择用于输入/输出操作的输入/输出设备。然后，将寄存器3设置为提供给门1的信号，寄存器3将表示输入/输出装置正在使用的信号发送给定时器4.该信号在规定的周期后提供给或门2 的时间由计时器4计数。然后，寄存器3由门2的输出复位。

6. 发明专利

JPS5622139A ADDRESS DESIGNATING DEVICE 失效
公开(公告)号：JPS5622139A
公开(公告)日：1981-03-02
申请号：JP9675579
申请日：1979-07-31
申请人： FUJITSU LTD
发明人： OOYAMA TOMONAGA
IPC分类号： G06F9/22 , G06F9/26
摘要： PURPOSE:To decrease the number of program steps and thus reduce the processing time, by forming the output only when the coincidence is secured between various types of condition signals and their expected values. CONSTITUTION:The condition signals sent from outside mean the interruption signals given from the higher-rank and lower-rank units among various types of condition signals C0-Cn. And the conditions given from the inside include the time- out or the like. The expected values EC0-ECn of signals C0-Cn are sent out from the control memory in the input/output control unit and based on the executing program to be stored in multibranch register 1. Then values EC0-ECn corresponding to signals C0-Cn are supplied to NOT exclusive OR gates 2(0)-2(n) respectively to obtain logic value ''1'' at each output only when the coincidence is secured between the supplied condition signal and the expected value. Thus the collation between the condition signal and its expected value is carried out com prehensively and simultaneously. As a result, a conventional large number of steps can be eliminated.

7. 发明专利

JPH054691B2 失效
公开(公告)号：JPH054691B2
公开(公告)日：1993-01-20
申请号：JP13353986
申请日：1986-06-09
申请人： FUJITSU LTD
发明人： MATSURA HIDEO , OOYAMA TOMONAGA
IPC分类号： G06F3/06 , C03B37/027 , G11B27/10

8. 发明专利

JPS62289976A DISK CONTROL SYSTEM 失效
公开(公告)号：JPS62289976A
公开(公告)日：1987-12-16
申请号：JP13352686
申请日：1986-06-09
申请人： FUJITSU LTD
发明人： MOMOSE HARUO , OOYAMA TOMONAGA
IPC分类号： G11B21/08 , G11B20/18
摘要： PURPOSE:To efficiently and quickly control a device by controlling restoration to the same record in accordance with control procedures of a positioning control means. CONSTITUTION:In a disk controller 20, a positioning control means 40 is provided where the processing, which extracts the off-track error during data write by error analysis reported from a pertinent device 3i, and procedures in accordance with which positioning to the same record as a designated record is controlled in case of report of the off-track error are stored. The control means 40 instructs the device 3i to be positioned to the designated record on a track, and restoration to the same record is controlled in accordance with control procedures in the means 40 if the off-track error during data write which is generated by residual oscillation or the like after positioning of a positioning mechanism in the device 3i is reported.

9. 发明专利

JPS61267123A DISK CONTROLLING DEVICE 失效
公开(公告)号：JPS61267123A
公开(公告)日：1986-11-26
申请号：JP10961085
申请日：1985-05-22
申请人： FUJITSU LTD
发明人： OOYAMA TOMONAGA , MOMOSE HARUO
IPC分类号： G06F3/06 , G11B20/18
摘要： PURPOSE:To execute retrying easily even when an overrun occurs in the second and succeeding records by storing the first count field position of plural records. CONSTITUTION:When a disk controlling device receives a command for continuous processing of plural records, the controlling device starts a specified disk device to make data processing of plural records, and prepares a processing completion signal 2 and a count field completion signal 3 every time each record processing is completed. On the other hand, a gate signal preparing section 33 stores count field position data 4 in a memory 35 utilizing the signal 1 and signals 2, 3 that indicate acceptance of the command. Accordingly, even when an overrun occurs in the second and succeeding records, it is positioned at the position of the first record and retrial processing can be executed.

10. 发明专利

JPS61216017A DISK CONTROLLER 失效
公开(公告)号：JPS61216017A
公开(公告)日：1986-09-25
申请号：JP3797385
申请日：1985-02-27
申请人： FUJITSU LTD
发明人： OOYAMA TOMONAGA
IPC分类号： G06F3/06 , G06F9/445 , G06F13/00
摘要： PURPOSE:To eliminate the misrecognition of a host device by inhibiting state information on a retrial state from being reported by an inhibiting means while the host device is in process of initial program loading. CONSTITUTION:An OR circuit 6 ORs a system reset signal 1' that a CPU 1 outputs in initial program loading (IPL) with a read LPL command 2' and outputs its result to a timer 7 and an FF 8, which are reset. The timer 7 starts counting with a specific clock 4' and sends out a carry 5' to the FF 8 when counting up to a set value. Consequently, the FF 8 sends out an ON signal from its output terminal Q to an AND circuit 9. The circuit 9 ANDs a signal 3' inputted from a switch 3a with the signal from the terminal Q of the FF 8 and sends reporting permit information 6' back to a specific position of a disk controller 3 when the AND condition is satisfied; and this information 6; is confirmed by the controller 3 to inform the CPU11 of state information as statistical information on hardware retrial, etc.

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