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1. 发明专利

JPS6155750A Alarm processing of computer system 失效
标题翻译：计算机系统报警处理
公开(公告)号：JPS6155750A
公开(公告)日：1986-03-20
申请号：JP17866584
申请日：1984-08-28
申请人： Fujitsu Ltd
发明人： NOSAKA TAIJI
IPC分类号： G06F11/30 , G06F11/07
CPC分类号： G06F11/0703
摘要： PURPOSE:To handle automatically a system-down without a human touch as much as possible by providing an alarm processing part for issuing the alarm in accordance with the type of the alarm and the operating state of a system. CONSTITUTION:A processor 50 of a power source control part 5 monitors alarms from interfaces 52 and 53, and grasps the operating state of a computer system 1 when the alarm interruption occurs. Since a trouble is considered due to an abnormal power source system when the alarm occurs at the time of turning on a power source, a fan system of a power source unit 3 is checked to be normal or not. After the system is abnormal to investigate a flag in a memory 51, the unit 3 is turned off through the interface 52 to activate an alternative power source unit 4. When the alarm does not occur at the time of turning on a power source, the action state from a service processor 2 is received and the operation is judged to be under the automatic running. Then, since an operator does not exist, a power source is turned off with respect to the abnormality except a main frame after the JOB termination.
摘要翻译：目的：通过提供根据报警类型和系统运行状态发出报警的报警处理部分，尽可能多地自动处理无需人为触摸的系统关闭。构成：电源控制部5的处理器50监视来自接口52,53的报警，并且在发生报警中断时掌握计算机系统1的运行状态。由于当在接通电源时发生报警时由于异常电源系统而考虑到故障，所以检查电源单元3的风扇系统是否正常。在系统异常以检查存储器51中的标志之后，通过接口52关闭单元3以激活替代电源单元4.当打开电源时不发生报警时，接收到来自服务处理器2的动作状态，并且判断该操作处于自动运行状态。然后，由于操作者不存在，所以在作业终止之后，关于除了主框架之外的异常而关闭电源。

2. 发明专利

JPS57150042A READING AND WRITING SYSTEM OF INSTRUCTION 失效
公开(公告)号：JPS57150042A
公开(公告)日：1982-09-16
申请号：JP3478481
申请日：1981-03-10
申请人： FUJITSU LTD
发明人： NOSAKA TAIJI , OZAWA HIDEKIYO
IPC分类号： G06F9/45 , G06F9/06 , G06F9/44 , G06F15/16 , G06F15/177
摘要： PURPOSE:To facilitate both the discrimination and assembly of a program, by converting a machine word instruction read out of a main body processor into an assembler instruction and displaying it to a service processor to realize an input of an assembler instruction. CONSTITUTION:The communication is carried out between a main body processor 1 and a service processor 3 via a computer console interface line 10. The data read out of the processor 1 is displayed on a display 6. A keyboard 7 is used to supply a data or a command to the processor 3. An adverse converting means 4 converts a machine word instruction of binary display read out of a main storage 2 into an assembler instruction. A converting means 5 converts the assembler instruction supplied from the keyboard 7 into a machine word instruction of binary display.

3. 发明专利

JPS6213688B2 失效
公开(公告)号：JPS6213688B2
公开(公告)日：1987-03-28
申请号：JP16186379
申请日：1979-12-13
申请人： FUJITSU LTD
发明人： NOSAKA TAIJI
IPC分类号： G06F3/153 , G06F3/14 , G09G5/00

4. 发明专利

JPS5580893A MEMORY DEVICE 失效
公开(公告)号：JPS5580893A
公开(公告)日：1980-06-18
申请号：JP14883078
申请日：1978-12-01
申请人： FUJITSU LTD
发明人： NOSAKA TAIJI
IPC分类号： G06F12/16 , G11C29/00
摘要： PURPOSE:To remedy the steady fault of the memory element in a simple and economical way by giving inversion to each bit of the data read out when the inverse display bit of the data region is on and at the reading time, thus increasing the efficiency for operation of the computer. CONSTITUTION:Inverse display bit 11 is provided every inversion circuit of the data and data reion 12, and each bit value of the data is written after inversion into region 12 which is incapable of the steady writing. At the same time, inverse display bit 11 of region 12 is turned on previously, and then each bit of the reading data is inverted if bit 11 is on at the reading time. As a result, the steady fault can be remedied for the memory element in a simple and economical way, thus ensuring a high-efficiency operation for the computer.

5. 发明专利

JPS5532208A MEMORY CONTROL SYSTEM 失效
公开(公告)号：JPS5532208A
公开(公告)日：1980-03-06
申请号：JP10259178
申请日：1978-08-23
申请人： FUJITSU LTD
发明人： NOSAKA TAIJI
IPC分类号： G06F12/16 , G06F11/16 , G11C29/00
摘要： PURPOSE:To eliminate the need of the replacement of a component of a main memory even if, a fault occurs to the memory, by providing an error memory and substitute memory. CONSTITUTION:When an uncorrectable error occurs and error address Ej is detected, processor 5 writes ''1'' on disabling bit 12 of address Ej under the control of microprogram 4 and also writes ''1'' on substitute bit 11 of address Ej+1 while writing substitute address Aj of substitute memory 3 in address Ej+1. After the execution of arithmetic of Aj+2 to Aj and i+1 to i, the error bit in address (i) of error memory is set to ''1'' and error address Ej is stored. Therefore, the replacement of a component of the memory is unneded even if the main memory gets out of order.

6. 发明专利

JPS57111753A DISPLAY SYSTEM 失效
公开(公告)号：JPS57111753A
公开(公告)日：1982-07-12
申请号：JP18539980
申请日：1980-12-29
申请人： FUJITSU LTD
发明人： NOSAKA TAIJI
IPC分类号： G06F11/22 , G06F11/07
摘要： PURPOSE:To display a state even if a service processor has been downed, by converting a counting value to a scan-out address having a different value, in a system for displaying a state of a latch and a register in a processing device. CONSTITUTION:In case it is desired to scan out the inside of a block 12, a numerical value assigned to the block 12 is set to a fixed part 7a of an address counter 7 by a block setting circuit 9, and a counter part 7b is started. A counting value of the address counter 7 is inputted to a memory 4 as address information, and scan-out addresses a1, a2-an are generated. Subsequently, at first, status information of a latch is read out by being designated by the address a1, and is superposed on a scan-out data line (ls) of the right side end. In this case, when a signal of the data output line of the right side end becomes on, a latch state of the address a1 is displayed by a light emission diode 1 of the right side end. Subsequently, a latch state of the address a2 is read out, and is displayed by the second diode 1 from the right side end.

7. 发明专利

JPS5685152A DISPLAY BUFFER CONTROL SYSTEM 失效
公开(公告)号：JPS5685152A
公开(公告)日：1981-07-11
申请号：JP16186379
申请日：1979-12-13
申请人： FUJITSU LTD
发明人： NOSAKA TAIJI
IPC分类号： G06F3/153 , G06F3/14 , G09G5/00
摘要： PURPOSE:To avoid the waiting for vacancy of the main memory and thus increase the overall working efficiency of the control system, by installing a display exclusive buffer which is not connected to the common bus. CONSTITUTION:The signals of the address 1, data bus 2 and control bus 3 are received at the common bus transmission/reception circuit 4, and a comparison is given to these signals at the comparator 5 whether they mean the address of the display buffer 9 in the main memory. If these signals are within the address range, the exclusive memory control circuit 7 is actuated to write the same data as the buffer 9 into the display exclusive buffer 10 through the data bus 2. In this case, the reading circuit 12 has to wait until the end of writing. Thus no common bus nor the main memory are used for the reading for display refresh. Accordingly, the display buffer can be read and written directly via the processor. In addition, the using efficiency is never lowered for the common bus regardless of the reading of the display unit.

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