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1. 发明专利

JPS63318650A MEMORY ACCESS PROCESSING SYSTEM 失效
公开(公告)号：JPS63318650A
公开(公告)日：1988-12-27
申请号：JP15597987
申请日：1987-06-23
申请人： FUJITSU LTD
发明人： TAKEI MASAYOSHI , MURATA TAKESHI , NODA TAKAHITO , KAMISAKA YUJI , ABO KENICHI , NONOMURA KAZUYASU , NISHIMACHI RIYOUICHI , SAKURAI YASUTOMO
IPC分类号： G06F12/04
摘要： PURPOSE:To execute an inter-memory data transfer, etc. at a high speed, and also, to improve the efficiency for developing a software, the providing a multiplexer for fetching a desired data from a arbitrary position in a data consisting of plural which is read out of a memory. CONSTITUTION:A data consisting of plural bytes, which is read from a memory 8 is stored in a read buffer 2. Subsequently, in accordance with a micro- instruction which is read out of a ROM 7, a micro-instruction register (MIR) 6 controls a multiplexer 3, fetches the data from a position of X, Y or Z of the buffer 2 and supplies it to a processing part 4. The processing part 4 transfers and stores a result of executed prescribed processing in a write buffer 5, etc., and the data consisting of plural bytes which is stored in the buffer 5 is written in the memory 8. In such a way, by constituting the multiplexer 3 so that desired data can be read out from an arbitrary position of the consisting of plural bytes, which is stored in the buffer 2, an inter-memory data transfer, etc., can be executed at a high speed and the efficiency for developing a software can be improved.

2. 发明专利

JPS63285658A CIRCUIT FOR PREVENTING COLLISION OF DATA ON BUS 失效
公开(公告)号：JPS63285658A
公开(公告)日：1988-11-22
申请号：JP12150787
申请日：1987-05-19
申请人： FUJITSU LTD
发明人： ABO KENICHI , MURATA TAKESHI , NODA TAKAHITO , KAMISAKA YUJI , NONOMURA KAZUYASU , TAKEI MASAYOSHI , NISHIMACHI RIYOUICHI , SAKURAI YASUTOMO
IPC分类号： G06F13/36 , G06F3/00 , G06F13/00 , G06F13/376
摘要： PURPOSE:To improve the bus availability by inhibiting the transmission of data onto a bus for a period of a 1/2 clock cycle from a time point when a bus application permitting signal is received. CONSTITUTION:A novel control clock of a phase opposite to a clock is supplied to a timing production means 17 from a terminal B and the means 17 transmits an output permission timing signal (7) after a 1/2 clock cycle based on a bus application permitting signal supplied from a terminal C. Then a data transmission period production means 18 can transmit the bus output permitting signals (1) for a period of the multiple of integer as long as the 1/2 clock cycle based on the signal (7), the clock supplied from a terminal A and the bus application permitting signal. Thus a bus fight prevention cycle is set at a 1/2 clock cycle. As a result, the data can be transferred at high speed.

3. 发明专利

JPS6366647A INHIBITING CIRCUIT FOR REPLACEMENT OF CACHE MEMORY 失效
公开(公告)号：JPS6366647A
公开(公告)日：1988-03-25
申请号：JP21129986
申请日：1986-09-08
申请人： FUJITSU LTD
发明人： NONOMURA KAZUYASU , MURATA TAKESHI , NODA TAKAHITO , KAMISAKA YUJI , ABO KENICHI , TAKEI MASAYOSHI , NISHIMACHI RIYOUICHI , SAKURAI YASUTOMO
IPC分类号： G06F12/08
摘要： PURPOSE:To simplify investigation of the factor of a fault by providing an exclusive cache memory to each processor and inhibiting the rewriting of the cache memory when another processor rewrites a main memory in an investigation mode of the fault. CONSTITUTION:Each processor PC3 has its exclusive cache memory 2 and a monitor circuit 4 gives a rewrite permission signal to the memory 2 when another PC9 rewrites the data on a main memory 1 in the same address as the data copied in the memory 2. In a fault search mode, the PC9 sends the address of a flag register 13 to a bus 10 and at the same time sends a bit to a bus 11 to set the register 13. A decoder 12 decodes the address of the register 13 and sets the register 13 in an enable state. Then the register 13 sends 1 to a NOT circuit 14 and the circuit 14 sends 0 to an AND circuit 15. Therefore the circuit 15 inhibits the rewrite permission signal of the circuit 4. As a result, the situation is easily grasped in a fault search mode with no breakdown of the contents of the memory 2 even though the data on the memory 1 is rewritten by the PC9.

4. 发明专利

JPS62134753A MULTI-PROCESSOR SYSTEM 失效
公开(公告)号：JPS62134753A
公开(公告)日：1987-06-17
申请号：JP27472085
申请日：1985-12-06
申请人： FUJITSU LTD
发明人： TAKEI MASAYOSHI , MURATA TAKESHI , NODA TAKAHITO , KAMISAKA YUJI , ABO KENICHI , NONOMURA KAZUYASU , NISHIMACHI RIYOUICHI , SAKURAI YASUTOMO
IPC分类号： G06F15/16 , G06F15/177
摘要： PURPOSE:To obtain easily and also so as to be optionally variable a bus exclusive light priority circuit of every processor from the same circuit constitution, by setting so that a control input terminal of the priority circuit goes to a prescribed signal state, and supplying a signal to the control input terminal so that a bus exclusive light is determined by a desired control signal at every multi-processor. CONSTITUTION:A prescribed input terminal 121 of an exclusive right priority circuit 119 by the same constitution of each processor 113 is set to a prescribed signal state which is determined in advance, and also, a control signal 115 is supplied to every input terminal 121 of the processor 113 so that a priority right for giving an exclusive light to each processor can be determined. Accordingly, at every processor 113, a degree of priority for giving an exclusive right of the first bus 111 can be determined. By the exclusive right which is designated in such a way, each processor 113 executes a transfer of information by utilizing the first bus 111. Also, by a set state of a setting means 123 and a supply state of the control signal 115, the degree of priority for delivering the exclusive right to each processor 113 is determined.

5. 发明专利

JPS62119640A MACHINE LANGUAGE INSTRUCTION PRE-PROCESSING SYSTEM 失效
公开(公告)号：JPS62119640A
公开(公告)日：1987-05-30
申请号：JP26025585
申请日：1985-11-20
申请人： FUJITSU LTD
发明人： NODA TAKAHITO , KAMISAKA YUJI , TAKEI MASAYOSHI , NISHIMACHI RIYOUICHI , NONOMURA KAZUYASU , SAKURAI YASUTOMO , MURATA TAKESHI , KAMIMURA AKITOSHI
IPC分类号： G06F9/30 , G06F9/22
摘要： PURPOSE:To improve the processing speed by storing fetch data in plural registers by applications into plural registers simultaneously having the possibility of storing the data when a fetch timing comes. CONSTITUTION:The fetch data is stored simultaneously in plural registers having the possibility to store the data among plural registers by applications when the fetch timing comes before the discrimination result to which register the data are to be stored among the plural registers by applications in fetching a machine language instruction in an information processing unit of the microprogram system having plural registers by applications for storing a machine language instruction and storing and processing each part of the fetched machine language instruction into the registers by applications. Thus, an idle time as to the fetch operation is not caused.

6. 发明专利

JPS6245213A SYNCHRONIZATION SYSTEM FOR ASYNCHRONIZING SIGNAL 失效
公开(公告)号：JPS6245213A
公开(公告)日：1987-02-27
申请号：JP18548285
申请日：1985-08-22
申请人： FUJITSU LTD
发明人： NISHIMACHI RIYOUICHI , MURATA TAKESHI , KANEDA HIROYUKI , NODA TAKAHITO , KAMISAKA YUJI , TAKEI MASAYOSHI , NONOMURA KAZUYASU , KAMIMURA AKITOSHI , SAKURAI YASUTOMO
IPC分类号： H03K3/02 , G06F1/12 , G06F5/06 , G06F13/42 , H03K5/00
摘要： PURPOSE:To obtain a stable synchronizing signal with a simple circuit by providing a means selecting a clock to an FF circuit to which an asychronizing signal is applied in a cynchronizing system using 2-stages of the FF circuits. CONSTITUTION:A multiplex circuit 3 operated as a selection circuit is added to a clock terminal of the FF circuit 1. The multiplex circuit 3 is operated by depressing, e.g., a switch 3-1 by the operator while a double CLK controls the Ff circuit 1. If the FF circuit 1 has a large instable operation region and an undesired output is caused at a synchronizing signal D3 as an output of the FF circuit 2, the multiplex circuit 3 is changed over by the switch 3-1 to operate it by a CLK. Since the next clock is given to the instable operating region in this way, no undesired signal appears at the synchronizing signal D3. Thus, a stable synchronizing signal is obtained by a simple circuit.

7. 发明专利

JPS63311438A CONTROL CIRCUIT FOR DISCREPANCY OF STORE INSTRUCTION 失效
公开(公告)号：JPS63311438A
公开(公告)日：1988-12-20
申请号：JP14727587
申请日：1987-06-12
申请人： FUJITSU LTD
发明人： KAMISAKA YUJI , MURATA TAKESHI , NODA TAKAHITO , ABO KENICHI , TAKEI MASAYOSHI , NONOMURA KAZUYASU , NISHIMACHI RIYOUICHI , SAKURAI YASUTOMO
IPC分类号： G06F9/38
摘要： PURPOSE:To simplify the scale of hardware together with to decrease the number of both microinstructions and microinstruction executing steps by invalidating a flag and fetching unconditionally again an instruction in case of the original prefetched instruction is rewritten is detected. CONSTITUTION:In a prefetched state a discrepancy detecting circuit 5 detects whether the original prefetched instruction is rewritten or not based on the intra-page addresses and the number of bytes to be written among those addresses stored in an address register 4 as well as the intra-page addresses among those addresses stored in an instruction address register 3. When it is decided that said original instruction is rewritten, a flag 7 is invalidated. Then a main memory 8 is unconditionally read again and an instruction is stored in an instruction buffer 2 for execution of the processing in case an iBV selection signal outputted from the flag 7 is invalidated.

8. 发明专利

JPS63178353A MULTIPLEX VIRTUAL SPACE SYSTEM 失效
公开(公告)号：JPS63178353A
公开(公告)日：1988-07-22
申请号：JP1040287
申请日：1987-01-20
申请人： FUJITSU LTD
发明人： NODA TAKAHITO , MURATA TAKESHI , KAMISAKA YUJI , ABO KENICHI , TAKEI MASAYOSHI , NONOMURA KAZUYASU , NISHIMACHI RIYOUICHI , SAKURAI YASUTOMO
IPC分类号： G06F12/10
摘要： PURPOSE:To expand virtual spaces by forming the virtual spaces in respective running levels of a program and forming an area common to respective virtual spaces. CONSTITUTION:The virtual spaces, i.e. a virtual space (d) in case of S=0 and a virtual space (c) in case of S=1, are formed in respective running levels of the prescribed program in a computer and control table (a), (b) having bits indicating the area common to respective virtual spaces (c), (d) (for spaces S=0, S=1). Consequently, the virtual spaces can be comparatively easily multiplexed (expanded), the trough-put of an application program can be improved and an OS area can be also expanded.

9. 发明专利

JPS6326742A PROGRAM TRACER 失效
公开(公告)号：JPS6326742A
公开(公告)日：1988-02-04
申请号：JP17039486
申请日：1986-07-18
申请人： FUJITSU LTD
发明人： NISHIMACHI RIYOUICHI , NODA TAKAHITO , TAKEI MASAYOSHI , KAMISAKA YUJI , ABO KENICHI
IPC分类号： G06F11/28 , G06F11/34 , G06F15/16 , G06F15/177
摘要： PURPOSE:To read the trace data on the corresponding program tracer with a small quantity of hardware in a master/slave type multi-processor system, by adding a bidirectional interface to the program tracer and connecting the interface to the slave processor. CONSTITUTION:A master processor 2 gives an access to an internal register of a slave processor 3 and can read the storage contents of said register. A program tracer 4 is connected to the processor 3 via a bidirectional interface 5. Thus the processor 2 can read the record of the tracer 4 in the same way as that where an access is given to the internal register of the processor 3 just by allocating a part of said internal register to the tracer 4. Thus it is not required to provide an output device nor an output control part to each processor 2 as well as the hardware used to secure synchronism between the processor 2 and the tracer 4.

10. 发明专利

JPS62211767A INDIRECT ACCESS CONTROL SYSTEM 失效
公开(公告)号：JPS62211767A
公开(公告)日：1987-09-17
申请号：JP5530386
申请日：1986-03-12
申请人： FUJITSU LTD
发明人： NONOMURA KAZUYASU , MURATA TAKESHI , NODA TAKAHITO , KAMISAKA YUJI , ABO KENICHI , TAKEI MASAYOSHI , NISHIMACHI RIYOUICHI , SAKURAI YASUTOMO
IPC分类号： G06F12/02 , G06F12/00 , G06F12/06 , G06F15/16 , G06F15/17
摘要： PURPOSE:To access indirectly registers for many times in a short time by adding an automatic updating mechanism to an indirect address register of a subprocessor group when a main processor accesses a subprocessor. CONSTITUTION:When a main processor 1 accesses a subprocessor 2 through a common bus 3, an automatic updating mechanism 2-6 counts up an indirect address to update it and outputs the set clock of an indirect data (iDD) register 2-5 by the access to the iDD register 2-5. The automatic updating mechanism 2-6 counts up automatically the indirect address after the indirect address is set to the mechanism 2-6 once, and continuous access is performed with one indirect address setting.

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