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1. 发明专利

JPH02179997A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH02179997A
公开(公告)日：1990-07-12
申请号：JP33115988
申请日：1988-12-29
申请人： FUJITSU LTD
发明人： TSUCHIMOTO YUJI , MATSUZAKI YASURO , MUTO YOSHIKAZU , TAKAHASHI MASAKI
IPC分类号： G11C17/00 , G11C16/06 , H03K19/00 , H03K19/08
摘要： PURPOSE:To eliminate the delay of a read speed due to the decrease of a supply voltage by detecting the fluctuation of the supply voltage connected to a bit line, and changing the resistance value of a feeding path connected from a power source to the bit line according to the voltage fluctuation. CONSTITUTION:A circuit (DET) to detect the fluctuation of a supply voltage connected to bit lines (B1 to Bn) and a circuit (PC) to change the resistance value of the feeding path connected from a power source (Vcc) to the bit lines (B1 to Bn) according to the detected voltage fluctuation are provided. When the supply voltage (Vcc) is reduced, by decreasing the resistance value of the feeding path connected from the power source (Vcc) to the bit line (B1 to Bn), the shortage of a charging current for the bit line is compensated, and the voltage increase curve of the bit lines (B1 to Bn) is corrected. Thus the delay of the data read speed can be prevented.

2. 发明专利

JPH01303810A ELECTRON IC CIRCUIT 失效
公开(公告)号：JPH01303810A
公开(公告)日：1989-12-07
申请号：JP13366088
申请日：1988-05-31
申请人： FUJITSU LTD
发明人： MATSUZAKI YASURO , TSUCHIMOTO YUJI , TAKAHASHI MASAKI , MUTO YOSHIKAZU , NAITO TAKAMITSU
IPC分类号： H03K5/00 , H03K19/00 , H03K19/0175
摘要： PURPOSE:To always impress a constant voltage to the power source edge of an input circuit and to prevent the malfunction of an input part due to the fluctuation of a supply voltage even when the supply voltage is higher by inserting a constant voltage circuit between the power source edge and the supply voltage source of the input circuit. CONSTITUTION:In an input circuit 24 to supply an input signal to an electronic circuit main body, a constant voltage circuit 42 is inserted between the power source edge and the supply voltage source of the input circuit 24. Thus, since the constant voltage circuit 24 is arranged between the power source edge and the supply voltage source of the input circuit 24, even when the supply voltage is fluctuated and higher, a constant voltage is always impressed to the input circuit 24. Thus, the malfunction of the input circuit 24 due to the fluctuation of the supply voltage can be prevented.

3. 发明专利

JPH01146198A PROGRAMABLE READ ONLY MEMORY DEVICE 失效
公开(公告)号：JPH01146198A
公开(公告)日：1989-06-08
申请号：JP30333087
申请日：1987-12-02
申请人： FUJITSU LTD
发明人： MUTO YOSHIKAZU
IPC分类号： G11C17/00 , G11C16/02
摘要： PURPOSE:To make unnecessary a correspondence by an external writing device even when the size of a cell is changed and to surely execute a data writing by supplying only a signal for merely controlling whether the data writing is to be executed or not from the external writing device and generating a current for the writing at the internal part. CONSTITUTION:A gate circuit 6B in a program circuit 6 supplies an output current from a constant current circuit 6A to selective bit lines BL1-BLn according to the existence of a control signal WS for the writing in an output terminal 1 when any bit line is selected by a column decoder 5. Therefore, it is not necessary to supply the current for the writing from the external writing device, and it is enough to merely output the control signal for the writing from the external writing device. Thus, a troublesome correspondence by the writing device becomes completely unnecessary even when the size of the cell is changed, and the data writing can be executed surely.

4. 发明专利

JPH02131010A ADDRESS CHANGE DETECTING CIRCUIT 失效
公开(公告)号：JPH02131010A
公开(公告)日：1990-05-18
申请号：JP28427288
申请日：1988-11-10
申请人： FUJITSU LTD
发明人： MATSUZAKI YASURO , TSUCHIMOTO YUJI , MUTO YOSHIKAZU , TAKAHASHI MASAKI
IPC分类号： G11C11/41 , G11C8/18 , H03K5/1532
摘要： PURPOSE:To output an address change detection signal instantly by adopting the constitution such that a signal detecting a change in an address signal is extracted from a common connecting point among a field effect transistor(TR), a load means and a bipolar TR. CONSTITUTION:With TRs 12, 13 turned on respectively, since a base current flows to a base of a TR Q1 through a load means Z3, and the TRs 12, 13 in this order, the bipolar TR Q1 is turned on. With the bipolar TR Q1 turned on, the potential at a connecting point B among the TR 12, the TR Q1 and the load means Z3 goes to a low level. When a prescribed time elapses, no current flows to the base of the bipolar TR Q1 and the bipolar TR Q1 is turned off. Thus, the potential at the connecting point B rises gradually toward the power voltage VDD. Since the bipolar TR Q1 is completely turned off, the base charge of the bipolar TR Q1 is discharged via the load means Z4. Thus, a change detection signal descending steeply is obtained just after the address change point of time at the connecting point B.

5. 发明专利

JPH02111120A TTL INPUT CIRCUIT 失效
公开(公告)号：JPH02111120A
公开(公告)日：1990-04-24
申请号：JP26278988
申请日：1988-10-20
申请人： FUJITSU LTD
发明人： TSUCHIMOTO YUJI , MATSUZAKI YASURO , MUTO YOSHIKAZU , TAKAHASHI MASAKI
IPC分类号： H03K17/567 , H03K19/003 , H03K19/0175
摘要： PURPOSE:To improve the margin in the logic operation and to make the operation stable by switching a 1st p-channel transistor(TR) to be cut off or turned on if a prescribed potential difference applied between 1st and 2nd power lines is fluctuated. CONSTITUTION:A p-channel MOS TR Q3 is switched to be either in the cut-off state or in the ON state in the process of the fluctuation of a power voltage Vcc in the border of a prescribed level (6VF+VBE). Thus, the ratio of the conductance of TRs Q1-Q4 deciding an input threshold voltage changes as (combined conductance) gm1'/gm2 gm1/gm2 or vice versa at the border of the prescribed level. Thus, the fluctuation in the input threshold voltage is suppressed lower. That is, since the margin in the logic operation is increased, the input circuit is expected to offer a more stable operation as a Bi-CMOS input circuit.

6. 发明专利

JPH02247899A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH02247899A
公开(公告)日：1990-10-03
申请号：JP6834089
申请日：1989-03-20
申请人： FUJITSU LTD
发明人： MATSUZAKI YASURO , TSUCHIMOTO YUJI , MUTO YOSHIKAZU
IPC分类号： G11C17/14
摘要： PURPOSE:To decrease the load of transistors for absorbing program current and to improve the scale of integration by providing biasing means which reverse biases the diodes inserted onto the routes of the program currents only at the time of reading out. CONSTITUTION:The programming of data is executed in the following manner: Address signals A0 to An and a writing enabling signal PVCE are inputted and IPRG is added to one of output terminals O1 to O4, then this IPRG is poured through a separating circuit 17 and a writing circuit 16 into the memory cell (for example, M1) of a memory cell array 18 to break the p-n junction of the cell M1 and is thereafter absorbed into a transistor TR T1 for absorbing the program current of a decoder driver 12. V1 is outputted from a switch control circuit 20 and the respective switch elements S11 of the biasing means 19 are held in the off state at this time. Namely, the VCC and the cathode of the diode D11 is opened, the current flowing into the TR T1 is only the IPRG and only this current is absorbed. The pattern area of the TR T1 is, therefore, decreased and the scale of integration is improved.

7. 发明专利

JPH0264997A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH0264997A
公开(公告)日：1990-03-05
申请号：JP21606488
申请日：1988-08-30
申请人： FUJITSU LTD
发明人： MATSUZAKI YASURO , TSUCHIMOTO YUJI , MUTO YOSHIKAZU , TAKAHASHI MASAKI
IPC分类号： G11C17/00 , G11C16/06 , G11C17/14
摘要： PURPOSE:To speed up access time and to reduce power by providing an address change detecting circuit, a variable load circuit to change the magnitude of a load according to a detected signal from the address change detecting circuit, and a bit line selecting circuit to select plural bit lines according to an address signal. CONSTITUTION:When an address is switched, the output voltage of an address change detecting circuit 14 becomes an L level, the load of a variable load circuit 15 becomes small, and a bit line current becomes large. Consequently, when a written cell S1 is switched to an unwritten cell S2, the rise of bit line voltage is speeded up. Thus, the access time can be speeded up. On the other hand, under a stationary state in which the address is never switched, the output voltage of the address change detecting circuit 14 becomes an H level constantly, the load of the variable load circuit 15 becomes large, and the bit line current becomes small. Thus, the power can be reduced.

8. 发明专利

JPH03268298A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH03268298A
公开(公告)日：1991-11-28
申请号：JP6760490
申请日：1990-03-16
申请人： FUJITSU LTD
发明人： UENO KOJI , TSUCHIMOTO YUJI , MUTO YOSHIKAZU
IPC分类号： G11C17/00 , G11C7/10 , G11C16/06
摘要： PURPOSE:To stabilize output, and to prevent malfunction by keeping an output terminal in high impedance, and extracting a current to a second power supply side during the pulse generating period of a pulse generating means, and turning the output terminal into H or L at the time of the expiration of the period. CONSTITUTION:When an address signal is fixed, it is inputted to buffers 21, 24, and simultaneously, it is inputted to an ATD circuit 28, and an ATD pulse (L active) is generated, and is sent to a signal correction circuit 29 and an output circuit 31. In the circuit 29, a bipolar Tr 56 is turned ON, and the holding current (i) of H flows in a node B through a PMOS Tr 52, and the node B is clamped. In the circuit 31, an MOS Tr 76 is turned ON, and a Tr 75 is turned ON, and the Trs 72 to 74 are turned OFF, and the output terminal is turned into a high impedance state, and the current is extracted to a GND side, and the terminal is turned into GND potential. Next, when the ATD pulse is finished, the output terminal is turned into a level to be determined by the output level of a sense amplifier circuit 30. At that time, the node B is turned into L or H according to storage information selected by the memory part 28, and the current is sent to the output circuit 31, and the output terminal is turned into L or H.

9. 发明专利

JPH01305617A LOGICAL CIRCUIT 失效
公开(公告)号：JPH01305617A
公开(公告)日：1989-12-08
申请号：JP13611888
申请日：1988-06-02
申请人： FUJITSU LTD
发明人： TAKAHASHI MASAKI , MATSUZAKI YASURO , TSUCHIMOTO YUJI , MUTO YOSHIKAZU , NAITO TAKAMITSU
IPC分类号： H03K17/04 , H03K19/094 , H03K19/0944
摘要： PURPOSE:To obtain the driver circuit of a decoder, for which a constant current can always flow to a front step gate, by connecting the gate of a transistor through a diode to a power source voltage and through a resistor to a ground line. CONSTITUTION:A Zener diode DZ and a load resistor R are connected between a gate (control electrode) G of a wring transistor TP, which constitutes the front step gate circuit of the driver circuit in the decoder, and a power source bus PVCE (VCC). These Zener diode DZ and load resistor R are operated as a constant current circuit to the gate voltage of the transistor TP. Thus, even when a power source voltage is different at the time of writing and reading, the front step gate can always absorb the current of a constant value. Then, a pattern area can be prevented from being enlarged on the basis of the current capacity increase processing of a transistor for front step gate or an access time can be prevented from being delayed on the basis of pressure resistance improving processing.

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