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1. 发明专利

JPH04156039A AUTOMATIC ABSENCE MODE ON/OFF TYPE AUTOMATIC ANSWERING TELEPHONE SET 失效
公开(公告)号：JPH04156039A
公开(公告)日：1992-05-28
申请号：JP28065790
申请日：1990-10-19
申请人： FUJITSU LTD
发明人： MAKIYAMA TAKAO , TAKAHASHI YUJI
IPC分类号： H04M1/64
摘要： PURPOSE:To sufficiently use an absence mode function by automatically turning on/off the absence mode function based on detection information from an external sensor which detects absence information, and automatically reproducing absence recording in the case of performing the absence recording when the absence mode function is turned off. CONSTITUTION:When the absence information is detected by the external sensor 6 and is inputted to an automatic answering telephone set 1, the absence mode function is automatically turned on by an absence mode control means 8. When an incoming call from the outside is received via a telephone line 2 at the time of setting an absence mode, a recording part 5 informs absence to a caller by performing a reproducing operation, while, the voice of the caller is recorded at need. Meanwhile, when a user comes back and the information is detected by the external sensor 6, the absence mode is automatically turned off by the means 8, and when the absence recording is performed on the recording part 5 by recording/reproducing control means 9, it is automatically reproduced, and is informed to the user coming back. Thereby, the absence mode function can be sufficiently used.

2. 发明专利

JPS6234133A LIQUID CRYSTAL DISPLAY DEVICE 失效
公开(公告)号：JPS6234133A
公开(公告)日：1987-02-14
申请号：JP17477085
申请日：1985-08-08
申请人： FUJITSU LTD
发明人： MAKIYAMA TAKAO
IPC分类号： G02F1/133 , G09G3/18
摘要： PURPOSE:To adjust brightness automatically according to variation in ambient temperature and to stabilize display quality by supplying a source voltage for driving liquid crystal after the voltage division by a resistance which has a large resistance value increase based upon a temperature coefficient and a resistance which has a smaller resistance value than said resistance. CONSTITUTION:A liquid crystal display device 2 is controlled and driven with a display command from a control part 1. Driving power sources 10 and 11 are connected between terminals 4 and 6 of the display device and the connection point of the power sources 10 and 11 and a terminal 3 are ground. Further, the series circuit of resistances 7 and 8 is connected between the terminals 4 and 6 and temperature coefficients of the resistance values of the resistances 7 and 8 are so determined that the resistance 7 is larger than the resistance 8. The connection point of those resistances 7 and 8 is connected to a terminal 5 and the voltage between the terminals 5 and 6 is supplied as the driving voltage 12 to the display device 2. Then, the voltage divided by the resistances 7 and 8 having said temperature coefficient relation is sued as the driving voltage 12 to adjust the brightness automatically according to the variation in the ambient temperature.

3. 发明专利

JPS61101142A Data protection circuit 失效
标题翻译：数据保护电路
公开(公告)号：JPS61101142A
公开(公告)日：1986-05-20
申请号：JP22336584
申请日：1984-10-24
申请人： Fujitsu Ltd
发明人： MAKIYAMA TAKAO
IPC分类号： H04L25/38 , H04L1/00
摘要： PURPOSE: To eliminate a data error generated on a transmission line by allocating a data from a data terminal device of a low speed at the transmission side into a frame, transmitting a frame having the same data content for plural number of times, taking majority decision of the frame data received for plural number of times at the reception side and using it as a reception data and transmitting it to a data terminal device of low speed at the reception side.
CONSTITUTION: A data from a low speed data terminal device 1 enters a sampling circuit 2-1, a bit signal obtained from the sampling is fed to a transmission side shift register 2-3, a synchronizing flag bit from a synchronizing flag generating circuit 2 is added at plural n-bit, and the result is transmitted for plural number M of times as a high speed synchronizing data. A reception side data adaptor 5 stores the plural M-set of frame signals to a signal shift register 5-1 one after another, a synchronism detection circuit 5-2 detects the synchronizing flag bit and moves only the reception data to a datalatch circuit 5-3a one after another. The data latch circuit 5-3a applies majority decision to the M-set of frame data and its output data is inputted to an output shift register 5-4.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：为了消除传输线上产生的数据错误，通过将数据从传输侧的低速数据终端设备分配到一个帧中，发送具有相同数据内容的帧多次，以多数决定在接收侧接收多次的帧数据，并将其用作接收数据，并将其发送到接收侧的低速数据终端设备。构成：来自低速数据终端装置1的数据进入采样电路2-1，从采样获得的位信号馈送到发送侧移位寄存器2-3，来自同步标志产生电路2的同步标志位以多个n位添加，并且将结果作为高速同步数据发送多次M次。接收侧数据适配器5将多个M组的帧信号一个接一个地存储到信号移位寄存器5-1，同步检测电路5-2检测同步标志位，并且仅将接收数据移动到数据分配电路5 -3a一个接一个数据锁存电路5-3a将多数决定应用于帧数据的M组，其输出数据被输入到输出移位寄存器5-4。

4. 发明专利

JPS59107669A Digital exchange system of asynchronous data 失效
标题翻译：无数据数字交换系统
公开(公告)号：JPS59107669A
公开(公告)日：1984-06-21
申请号：JP21646482
申请日：1982-12-10
申请人： Fujitsu Ltd
发明人： SUTANI YOSHIAKI , NAITOU SHIYUNICHI , KOBAYASHI YUKIO , MINAMITANI EIJI , MAKIYAMA TAKAO , KODAIRA SHIGEO
IPC分类号： H04L25/02
CPC分类号： H04L25/0262
摘要： PURPOSE:To prevent overflow of data at a terminal interface by providing a hardware such as speed comparison circuit to an interface device at a transmission side so as to change a data transmission speed to a receiving side in response to the data transmission speed of a terminal device at the transmission side. CONSTITUTION:The interface device INFA at the transmission side is provided with a character assembling section CST, a speed comparison circuit COM and a reference speed clock generator and the data transfer speed from a data terminal device DTA is compared with a reference speed. When the transfer speed is faster through the comparison, the speed information is transmitted to an interface device INFB at the receiving side via a digital exchange network DNW. A speed bit is detected by a speed bit detector DFT of the device INFB so as to control a switching circuit SEL, and a clock generator is changed over from the standard clock generator to the maximum clock generator, the maximum clock is transmitted to a transfer circuit TRN and the transfer speed to the data terminal device DTB at the receiving side is quickened.
摘要翻译：目的：通过向发送侧的接口设备提供诸如速度比较电路的硬件来防止终端接口的数据溢出，以便根据终端的数据传输速度将数据传输速度改变到接收侧设备在传输侧。构成：发送侧的接口装置INFA具有字符组合部CST，速度比较电路COM和基准时钟发生器，并将来自数据终端装置DTA的数据传送速度与基准速度进行比较。当通过比较传送速度更快时，速度信息经由数字交换网络DNW被发送到接收侧的接口设备INFB。速度位由装置INFB的速度位检测器DFT检测，以控制开关电路SEL，并且时钟发生器从标准时钟发生器切换到最大时钟发生器，最大时钟被传送到传输电路TRN和接收侧的数据终端设备DTB的传送速度加快。

5. 发明专利

JPS57210754A SETTING SYSTEM FOR ORDER LINE 失效
公开(公告)号：JPS57210754A
公开(公告)日：1982-12-24
申请号：JP9623281
申请日：1981-06-22
申请人： FUJITSU LTD
发明人： KOJIMA TAKUTO , SHIBATA YUUJI , MAKIYAMA TAKAO
IPC分类号： H04M3/22 , H04M3/00 , H04Q1/20 , H04Q11/04
摘要： PURPOSE:To eliminate the need for an order line, by using a spare line to establish the order line. CONSTITUTION:A master station CO and a remote line concentration station RLU of a digital exchanger are connected with normal use and spare lines L1 and L2, subscribers S1-Sn of the RLU are digitized with a line concentration network RNW and can communcate with a master station subscribers S0 via a normal/spare selector SELR, one of digital trunks DTR1 and DTR2, one of lines L1 and L2, one of digital trunks DTC1 and DTC2, a normal/spare selector SELC, a digital channel network NW and a subscriber circuit LC. A telephone set for order line, typewriters MC and MR and TYPR and TYPC can be connected via order line circuits SLGR and SLGC only when the line L1 is used for communication.

6. 发明专利

JPS63257418A ELECTRIC SOURCE LINKAGE SYSTEM 失效
公开(公告)号：JPS63257418A
公开(公告)日：1988-10-25
申请号：JP9019987
申请日：1987-04-13
申请人： FUJITSU LTD
发明人： MAKIYAMA TAKAO , MINAMITANI EIJI , NAITO SHUNICHI
IPC分类号： H02J1/00 , H04Q3/58

7. 发明专利

JPS60198941A TRANSMISSION CONTROL SYSTEM 失效
公开(公告)号：JPS60198941A
公开(公告)日：1985-10-08
申请号：JP5469484
申请日：1984-03-22
申请人： FUJITSU LTD
发明人： MAKIYAMA TAKAO , OZAWA YUKIO
IPC分类号： H04M11/06 , H04L13/00 , H04L29/08 , H04M11/00
摘要： PURPOSE:To transmit a signal without distortion by transmitting a sampling rate at the transmission side to a terminal device to be called to make a sampling clock at both terminal devices identical to each other. CONSTITUTION:Plural terminal devices 3, 3' are connected to a private branch of exchange PBX via interface devices IF2, 2'. A timing circuit 22 of a clock pulse of the device IF is preset so that the sampling rate is changed to a prescribed value and a transmission/reception circuit 23 transmits/receives change information of the sampling rate. The circuits 22, 23, a switch 28 and a gate G are controlled by a microprocessor 21. Then the sampling rate of the terminal device of the transmission side is transferred to a terminal device to be called, the sampling clock at both the terminal devices is made identical mutually under the control of the processor 21 to transmit a signal without distortion.

8. 发明专利

JPS5995753A DATA TRANSFER SYSTEM 失效
公开(公告)号：JPS5995753A
公开(公告)日：1984-06-01
申请号：JP20660382
申请日：1982-11-25
申请人： FUJITSU LTD
发明人： MINAMITANI EIJI , MAKIYAMA TAKAO
IPC分类号： H04L25/40 , G06F17/40 , H04L25/45
摘要： PURPOSE:To reduce the number of signal lines by simplifying the constitution of a receiving section without the need of a start bit detecting circuit and a counter, in transferring a code representing one character. CONSTITUTION:A data adding a start bit and a stop bit of the same sign before and after the bit string constituting a character code transmitted from a data transmission section is stored sequentially in a register SR by controlling the shift register SR with a clock transmitted from a data transmission. The receiving of one character code is detected by the logical product of outputs from the position of the register SR where the start bit and the stop bit are to be stored at the end of one character code receiving and the receiving data stored in the register SR is extracted.

9. 发明专利

JPS5950647A Dial calling system 失效
标题翻译：拨号系统
公开(公告)号：JPS5950647A
公开(公告)日：1984-03-23
申请号：JP16130582
申请日：1982-09-16
申请人： Fujitsu Ltd
发明人： KOBAYASHI YUKIO , MINAMITANI EIJI , MAKIYAMA TAKAO , OZAWA YUKIO
IPC分类号： H04M1/27 , H04M1/272 , H04M1/2745
CPC分类号： H04M1/2725
摘要： PURPOSE:To improve the service while keeping the function of an exchange as it is, by storing a number transmitted from a telephone set, and transmitting the number after adding a numeral automatically when an opposite party is busy. CONSTITUTION:In calling a telephone set 1 and selecting a telephone number of a called party, the number is transmitted to an exchange PBX. The number is stored in a storage device 4 in an adaptor. A detecting circuit 5 monitors whether a busy tone is returned from a PBX or a dial tone is returned. When the busy tone is detected, a hooking control circuit 9 is started. As a result, the calling is stopped once and the next calling is attained again. Numeral 1 is added to the number stored in the storage device and the next calling is attained. Thus, other telephone set positioned near the opposite party is called automatically.
摘要翻译：目的：通过存储从电话机发送的号码来保持交换机的功能，同时在对方忙时自动添加数字之后发送号码，来改善业务。规定：在呼叫电话机1并选择被叫方的电话号码时，将号码发送到交换机PBX。该号码存储在适配器中的存储设备4中。检测电路5监视是否从PBX返回忙音，或者返回拨号音。当检测到忙音时，起动控制电路9。结果，呼叫被停止一次，再次进行下一个呼叫。将数字1添加到存储装置中存储的号码中，并进行下一次呼叫。因此，定位在对方附近的其他电话机被自动调用。

10. 发明专利

JPS5799854A MASTER ERROR EDITING SYSTEM 失效
公开(公告)号：JPS5799854A
公开(公告)日：1982-06-21
申请号：JP17701080
申请日：1980-12-15
申请人： FUJITSU LTD
发明人： ISHIKAWA HIROSHI , SUTANI YOSHIAKI , MAKIYAMA TAKAO
IPC分类号： H04M3/22 , H04M3/08 , H04Q1/22
摘要： PURPOSE:To modify fault information, which should be included in a master error, rapidly by attaining access to a refresh memory, wherein data are written in prescribed addresses successively, and a control memory at the same time by the same address signal. CONSTITUTION:Various pieces of information are transmitted from devices (a)- (m) on time-division basis and then written successively in addresses, selected by an address selector AS, of a refresh memory RM. Then, they are read in the order of writing to the RM, and the contents of a control memory CM are also read with the same addresses as those of the RM, thereby opening and closing a gate G by the outputs. Only the flag of fault information to be monitored among pieces of information from the RM is sent to a processor SPR through the gate G. Every time the gate G is opened, the SPR edits a master error ME whose address is written in the memory. To specify the information to be monitored, a 1 is only written in the corresponding address of the CM through the SPR, so it is modified freely and rapidly.

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