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1. 发明专利

JPS59117896A Digital exchange system 失效
标题翻译：数字交换系统
公开(公告)号：JPS59117896A
公开(公告)日：1984-07-07
申请号：JP23305682
申请日：1982-12-24
申请人： Fujitsu Ltd
发明人： SUTANI YOSHIAKI , KODAIRA SHIGEO
IPC分类号： H04Q11/04
CPC分类号： H04Q11/0478
摘要： PURPOSE:To regenerate medium and high speed data in a correct sequence by controlling a buffer memory in a digital exchange so as to make the amount of delay of the data through the N-sets of path. CONSTITUTION:When a call to be transmitted is generated from a high/medium data trunk DT1 to a high/medium speed data trunk DT2, a central controller CPR controls a time division network TDSW to set two paths and transmits a set command signal to the trunks DT1, DT2. A selector SEL of the trunk DT1 selects phase information and transmits it to a phase adjusting circuit PC of the trunk DT2, then the phase adjusting circuit PC detects the amount of delay of the set path. The reading timing of the phase adjusting circuit PC is decided depending on the amount of delay. Thus, the timing of data through each path is made identical, allowing to reproduce the high/medium speed data in the correct sequence from a multiplexer MPX.
摘要翻译：目的：通过控制数字交换机中的缓冲存储器，以正确的顺序重新生成中高速数据，以便通过N组路径使数据的延迟量达到最大。构成：当从高/中数据中继线DT1到高/中速数据中继线DT2生成要发送的呼叫时，中央控制器CPR控制时分网络TDSW来设置两条路径，并将设置的命令信号发送到干线DT1，DT2。中继线DT1的选择器SEL选择相位信息并将其发送到中继线DT2的相位调整电路PC，然后相位调整电路PC检测设定路径的延迟量。相位调整电路PC的读取定时取决于延迟量。因此，通过每个路径的数据的定时是相同的，允许从多路复用器MPX以正确的顺序再现高/中速数据。

2. 发明专利

JPS59107669A Digital exchange system of asynchronous data 失效
标题翻译：无数据数字交换系统
公开(公告)号：JPS59107669A
公开(公告)日：1984-06-21
申请号：JP21646482
申请日：1982-12-10
申请人： Fujitsu Ltd
发明人： SUTANI YOSHIAKI , NAITOU SHIYUNICHI , KOBAYASHI YUKIO , MINAMITANI EIJI , MAKIYAMA TAKAO , KODAIRA SHIGEO
IPC分类号： H04L25/02
CPC分类号： H04L25/0262
摘要： PURPOSE:To prevent overflow of data at a terminal interface by providing a hardware such as speed comparison circuit to an interface device at a transmission side so as to change a data transmission speed to a receiving side in response to the data transmission speed of a terminal device at the transmission side. CONSTITUTION:The interface device INFA at the transmission side is provided with a character assembling section CST, a speed comparison circuit COM and a reference speed clock generator and the data transfer speed from a data terminal device DTA is compared with a reference speed. When the transfer speed is faster through the comparison, the speed information is transmitted to an interface device INFB at the receiving side via a digital exchange network DNW. A speed bit is detected by a speed bit detector DFT of the device INFB so as to control a switching circuit SEL, and a clock generator is changed over from the standard clock generator to the maximum clock generator, the maximum clock is transmitted to a transfer circuit TRN and the transfer speed to the data terminal device DTB at the receiving side is quickened.
摘要翻译：目的：通过向发送侧的接口设备提供诸如速度比较电路的硬件来防止终端接口的数据溢出，以便根据终端的数据传输速度将数据传输速度改变到接收侧设备在传输侧。构成：发送侧的接口装置INFA具有字符组合部CST，速度比较电路COM和基准时钟发生器，并将来自数据终端装置DTA的数据传送速度与基准速度进行比较。当通过比较传送速度更快时，速度信息经由数字交换网络DNW被发送到接收侧的接口设备INFB。速度位由装置INFB的速度位检测器DFT检测，以控制开关电路SEL，并且时钟发生器从标准时钟发生器切换到最大时钟发生器，最大时钟被传送到传输电路TRN和接收侧的数据终端设备DTB的传送速度加快。

3. 发明专利

JPS5950641A Multiplex data group unit exchange system 失效
标题翻译：多重数据组单元交换系统
公开(公告)号：JPS5950641A
公开(公告)日：1984-03-23
申请号：JP16130482
申请日：1982-09-16
申请人： Fujitsu Ltd
发明人： OZAWA YUKIO , NAITOU SHIYUNICHI , SUTANI YOSHIAKI , KODAIRA SHIGEO
IPC分类号： H04Q11/04 , H04L12/52
CPC分类号： H04L12/52
摘要： PURPOSE:To reduce the time of synchronism establishment and to start quickly communication, by using a predetermined bit for the transmission of a discriminating code of information transmitted terminal and using the rest as the transmission of information addressed to the terminal. CONSTITUTION:A serial/parallel converting section 7 converts receiving information into the parallel form of n bits, transmits it to a parallel/serial converting section 9, a designated code generating section 8 generates a designation code of m bits corresponding to a discriminating code of a receiving information transmitted terminal DR and transmits it to a converting section 9, which converts the designation code of m bits and the information of n bits into a 1-bit serial code and transmits it to a multiplex separating circuit DMPX. On the other hand, a serial/parallel converting section 10 of the DMPX converts a 1-bit serial code transmitted via a channel CH into a parallel form, and the m bits are transmitted to a decoder 11 and the n bits are to a parallel/serial converting section 12, respectively. The decoder 11 analyzes the designating code of m bits to discriminate the information transmitted address DR and to make a corresponding gate G conductive. The converting section 12 converts the information of n bits into a serial form and transmits it to the terminal DR.
摘要翻译：目的：为了减少同步建立的时间并开始快速通信，通过使用预定的比特来发送识别码的发送终端，并将其余的作为发送到终端的信息的发送。构成：串行/并行转换部分7将接收信息转换为并行形式的n位，将其发送到并行/串行转换部分9，指定代码生成部分8产生对应于鉴别码的m位的指定码接收信息发送终端DR并将其发送到转换部分9，转换部分9将m比特的指定码和n比特的信息转换为1比特串行码，并将其发送到多路复用分离电路DMPX。另一方面，DMPX的串行/并行转换部分10将经由信道CH发送的1比特串行码转换成并行形式，并将m比特发送到解码器11，并且n比特是并行的 /串转换部分12。解码器11分析m比特的指定码以区分信息发送地址DR并使相应的门G导通。转换部12将n位的信息转换为串行形式并将其发送到终端DR。

4. 发明专利

JPS5941993A Composite exchange system 失效
标题翻译：复合交换系统
公开(公告)号：JPS5941993A
公开(公告)日：1984-03-08
申请号：JP15193782
申请日：1982-09-01
申请人： Fujitsu Ltd
发明人： OZAWA YUKIO , NAITOU SHIYUNICHI , SUTANI YOSHIAKI
IPC分类号： H04L12/64 , H04Q11/04
CPC分类号： H04Q11/04
摘要： PURPOSE:To raise the utilizing efficiency of a trunk line, by connecting each digital service unit to an input of a multi-frame converting trunk through a digital channel device, and connecting an output to a digital trunk through said channel device. CONSTITUTION:A call signal of a telephone set T is encoded to a single frame of a unified bearer rate through a hybrid HYB, and is inputted and outputted to and from a digital channel device (DNW) of a telephone exchange SW. Data terminal equipments DE1-DEn send out a data of a low speed bearer rate, and it is converted to a data of a single frame of the unified bearer rate by digital service units DSU1-DSUn and is inputted to the DNW. Subsequently, it is inputted to a multi-frame converting trunk MUX TRK and is multiplexed to a multi-frame. An output line LO is connected to a digital trunk DT through the DNW, for instance, is multiplexed by time division together with a channel from the telephone set, is sent out to a trunk line L, and the utilizing efficiency can be raised.
摘要翻译：目的：提高中继线的利用效率，通过数字通道设备将每个数字业务单元连接到多帧转换中继线的输入，并通过所述通道设备将输出连接到数字中继线。构成：电话机T的呼叫信号通过混合HYB被编码为统一承载速率的单个帧，并被输入并从电话交换机SW的数字信道设备（DNW）输出。数据终端设备DE1-DEn发送低速承载速率的数据，并由数字业务单元DSU1-DSUn转换为统一承载速率的单帧数据，并输入到DNW。随后，将其输入到多帧转换中继MUX TRK，并被多路复用为多帧。输出线路LO通过DNW连接到数字中继线DT，例如，与电话机的信道一起被时分复用，被发送到中继线路L，并且可以提高利用效率。

5. 发明专利

JPS5854769A CHANNEL RESET SYSTEM 失效
公开(公告)号：JPS5854769A
公开(公告)日：1983-03-31
申请号：JP15454981
申请日：1981-09-29
申请人： FUJITSU LTD
发明人： OZAWA YUKIO , KOUNO HISAO , SUTANI YOSHIAKI
IPC分类号： H04M3/22 , H04Q11/04
摘要： PURPOSE:To reset a channel in a short time, by switching the clear/write control between inactive memory and a channel hold memory in response to the failure mode, in restart processing after the generation of a failure of a time division channel set. CONSTITUTION:A forward channel memory SPMF, a backward channel memory SPMB, an inactive memory IM controlling a busy idle of a channel performing the write control of each channel memory at each channel, and a channel storage memory HLM controlling the channel assignment, are provided in a titled system. The clear control for the memory IM, and write of the HLM and all addresses can be done. At the restart after the restoration of a failure, the clear and write control for the memory IM and the HLM are switched depending on a failure mode to reset the channel.

6. 发明专利

JPS5654154A TEST METHOD FOR DIGITAL SIGNAL GENERATOR 失效
公开(公告)号：JPS5654154A
公开(公告)日：1981-05-14
申请号：JP13111579
申请日：1979-10-11
申请人： FUJITSU LTD
发明人： KOBAYASHI YUKIO , SUTANI YOSHIAKI , OZAWA YUKIO
IPC分类号： H04M3/26 , H04M3/24 , H04M19/02
摘要： PURPOSE:To enable the detection of failure in hardware, by sequentially comparing the data at two time point data corresponding to a given period and the next one and producing alarm if there is any disagreement. CONSTITUTION:The output data from a digital signal generator 1 is stored in a register 3 for a certain time. Further, a data is picked up from the register 3 according to the timing pulse from a timing circuit 2, it is compared with the output data at a comparator 4 with a delay of one or a half period from the digital signal generator 1, and the agreement of the both is detected, and if disagreement is found, alarm is produced.

7. 发明专利

JPS6392135A DIGITAL SUBSCRIBER LINE TRANSMISSION SYSTEM 失效
公开(公告)号：JPS6392135A
公开(公告)日：1988-04-22
申请号：JP23754886
申请日：1986-10-06
申请人： FUJITSU LTD
发明人： SUTANI YOSHIAKI , MINAMITANI EIJI
IPC分类号： H04B3/04 , H04L5/16 , H04M3/18 , H04Q3/42
摘要： PURPOSE:To eliminate crosstalk to a subscriber line and to reduce the power consumption of a ping-pong transmission system by varying the transmission level of a station burst signal according to whether or not the subscriber line is long. CONSTITUTION:The arrival period of a subscriber burst signal detected by a synchronizing circuit 20 is sent to a delay time detecting means 21 and compared with the transmission period of the station burst signal to finds a transmission delay time. Then a delay time detecting means 21 compares a prescribed transmission delay time corresponding to the length of the constant-length subscriber line with the found transmission delay time and starts a switching means 22 in case of deciding that the found delay time is longer than the prescribed transmission delay time to vary the transmission level of a transmission driver 11 to a transmission level corresponding to the subscriber line length. Thus, the local burst signal with the proper level is sent out to both a short-distance subscriber line and a long-distance subscriber line. Therefore, the crosstalk to the subscriber line is eliminated and the power consumption is reduced.

8. 发明专利

JPS61187452A BIT STRING DATA CONVERTING CIRCUIT 失效
公开(公告)号：JPS61187452A
公开(公告)日：1986-08-21
申请号：JP2701185
申请日：1985-02-14
申请人： FUJITSU LTD
发明人： YAZAWA SHIGEHIKO , SUTANI YOSHIAKI
IPC分类号： H04L25/38 , H04L13/00 , H04L29/06
摘要： PURPOSE:To prevent an erroneous operation that bit string data including a synchronizing signal is extracted and sent to a data terminal device by providing a means for detecting that plural sets of synchronizing signals sent from an opposite party are received fro a prescribed period and using a detection signal to reset a counter. CONSTITUTION:The circuit consists of a shift register (SR4) 12 of 16-bit length shifting a signal received in 48kbit/s from a separation section 3d one by one bit and storing it, a gate (G3)8b supervising 6 bits of a gate (G2)8a supervising a high-order 6 bits and generating a detection signal and generating a detection signal, a gate (G4)13 generating a detection signal when the gates 8a, 8b detect a synchronizing signal at the same time. Since a counter 9 is reset only when a synchronizing signal inserted before and after the original bit string data of 4-bit length sent from the separation section 3 is detected correctly, even when a synchronizing signal is in error, the mis-extraction of data is prevented.

9. 发明专利

JPS58171161A TESTING SYSTEM OF SPARE DIGITAL TERMINAL MODULE 失效
公开(公告)号：JPS58171161A
公开(公告)日：1983-10-07
申请号：JP5331282
申请日：1982-03-31
申请人： FUJITSU LTD
发明人： ASHIHARA SHIYUUICHI , SUTANI YOSHIAKI , KODAIRA SHIGEO
IPC分类号： H04M3/26 , H04M3/24 , H04Q11/04
摘要： PURPOSE:To make it possible to always check the normality of a digital terminal module held as a spare one by testing the folding operation of said digital terminal module. CONSTITUTION:In the spare digital terminal module DMT5, a channel signal separated from a demultiplexer DMPX by a back word subhighway S-HWB0 is branched and inputted to a selector SEL5. The channel signal separated to the highway S-HWB0 is selected by a central controlling device and inputted to the transmitting circuit XMT5 of the spare module DTM5 by the highway S-HWB5 through the selector SEL5 to be sent to the line side. Since a loop is formed by a switch l5, however, the channel signal is folded and received by a receiving circuit RCV5 and inputted to a data comparator COMP by the highway S-HWF5 through the selector SELT to check the normality.

10. 发明专利

JPS584419A BUS DIAGNOSING SYSTEM 失效
公开(公告)号：JPS584419A
公开(公告)日：1983-01-11
申请号：JP10256281
申请日：1981-06-30
申请人： FUJITSU LTD
发明人： KOUNO HISAO , SUTANI YOSHIAKI , MASUDA NOBUYUKI
IPC分类号： G06F11/20 , G06F11/22 , G06F13/00 , G06F15/16 , G06F15/177
摘要： PURPOSE:To perform a quick reconstitution of a system without causing any confusion to the using processor side, by carrying out the diagnosis and the detection of a fault for the input/output device of the 2nd group which caused the factor of the fault with a spare processor after separating a faulty bus from the using system. CONSTITUTION:A fault of the 1st using bus BO is detected by a bus supervisory circuit SVCO while a system is executing the 1st processor MPRO and the bus BO as the using ones. Then the fault is informed to the using procesor. As a result, the processor MPRO separates the input/output devices IOCi+1-IOCi+n of the 2nd group from the using processor among the input/output devices IOCO-IOCi+n. Then a spare processor MPR1 performs the diagnosis for the separated input/output devices of the 2nd group. Thus the faulty device is detected and the device caused a bus fault is separated from the using system. Then the system is reconstituted.

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