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1. 发明专利

JP2006245849A Communication apparatus 审中-公开
标题翻译：通讯设备
公开(公告)号：JP2006245849A
公开(公告)日：2006-09-14
申请号：JP2005056892
申请日：2005-03-02
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SASAGAWA YASUSHI , KAWARAI KENICHI , HIYAKUKAI MASAMI , TAKATORI TAKASHI
IPC分类号： H04L12/28 , H04B17/00 , H04L12/46 , H04L12/70
CPC分类号： H04L12/4645 , H04L12/462 , H04L69/40
摘要： PROBLEM TO BE SOLVED: To provide a communication apparatus for detecting a network fault by its own apparatus only with high accuracy without the need for interaction using the same protocol between its own apparatus and an opposite apparatus under a multi-vendor environment. SOLUTION: A tag-attached packet transmission/reception section 11 generates a tag-attached packet by attaching a tag to a packet, the tag being registered to ports of physical links L for the purpose of identifying a virtual LAN built up between its own apparatus 10 and an opposite apparatus 20, and transmits the resulting packet to the opposite apparatus 20 via one of the physical links L. Further, the tag-attached packet transmission/reception section 11 receives the tag-attached packet subjected to tunneling through the opposite apparatus 20 and transferred from the other of the physical links L. A fault detection section 12 monitors whether or not the transmitted tag-attached packet can be loop-back-received via any of the physical links L while being subjected to tunneling through the opposite apparatus 20 at both ends of the virtual link on the virtual LAN throughout of which the tag-attached packet flows so as to detect the occurrence of a fault. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种仅通过其自己的设备以高精度检测网络故障的通信设备，而不需要在多厂商环境下在其自己的设备和相对设备之间使用相同协议的交互。解决方案：附加标签的分组发送/接收部分11通过将标签附加到分组来生成附加标签的分组，该标签被登记到物理链路L的端口，以便识别在其自己的设备10和相对设备20，并且经由物理链路L之一将所得到的分组发送到对方设备20.此外，标签附加分组发送/接收部11接收经隧道通过的标签附加分组相对设备20并且从物理链路L中的另一个传送。故障检测部分12监视所发送的附加标签的分组是否可以经过任何物理链路L被环回接收，同时被隧道通过在虚拟LAN上的虚拟链路的两端处的相对装置20，其中标签附加包流动，以便检测故障的发生。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2005269059A Data repeater, repeating method and program 审中-公开
标题翻译：数据重复，重复方法和程序
公开(公告)号：JP2005269059A
公开(公告)日：2005-09-29
申请号：JP2004076593
申请日：2004-03-17
申请人： Fujitsu Ltd , 富士通株式会社
发明人： TSURUMI OSAMU , KAWARAI KENICHI , ENDO AKIO , UGAI KAZUKUNI , ASA AKIHIRO
IPC分类号： H04L12/437 , H04L12/26 , H04L29/08 , H04L29/14
CPC分类号： H04L12/437 , H04L67/14 , H04L69/40
摘要： PROBLEM TO BE SOLVED: To provide data repeater, repeating method and program in which a network trouble can be recovered at high speed by decreasing the number of interruption times of communication. SOLUTION: When the data repeater stores information for identifying its own device and a trouble occurs in a link connected with its own device, a port connected with that link is blocked. When the trouble occurred in the link is recovered, identification information of other device connected with that link is compared with stored identification information and then a decision is made whether its own device is set as a master node or not based on the comparison results. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供通过减少通信中断次数来提供高速恢复网络故障的数据中继器，重复方法和程序。解决方案：当数据中继器存储用于识别其设备的信息并且在与其自己的设备连接的链路中发生故障时，与该链路连接的端口被阻止。当恢复链路中的故障时，将与该链路相连的其他设备的识别信息与存储的识别信息进行比较，然后基于比较结果判断其自己的设备是否被设置为主节点。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2001339427A PACKET SWITCH, SCHEDULING DEVICE, ABANDONMENT CONTROL CIRCUIT, MULTICAST CONTROL CIRCUIT AND QOS CONTROLLER 失效
公开(公告)号：JP2001339427A
公开(公告)日：2001-12-07
申请号：JP2000124667
申请日：2000-04-25
申请人： FUJITSU LTD
发明人： KAWARAI KENICHI , TOMONAGA HIROSHI , MATSUOKA NAOKI , KATO TSUGIO
IPC分类号： H04L12/70 , H04L12/823 , H04L12/865 , H04L12/951 , H04L12/56 , H04L12/28
摘要： PROBLEM TO BE SOLVED: To perform QoS control, abandonment control and multicast control to a variable length packet at high speed with a little hardware scale. SOLUTION: In a packet dividing part 10, the variable length packet is divided into fixed length packets and in an input buffer part 12, a queue is stored by output lines and further by QoS classes. In this case, by mapping a large number of QoS classes only to two kinds of a band guarantee class for guaranteeing a designated band and a best effort class for distributing an excessive band, input side scheduling is provided by an inter-line scheduler 14. In an output buffer part 18, the variable length packet is assembled from the fixed length packets switched by a,switch part 16 and QoS control depending on a packet length is performed.

4. 发明专利

JPH10247924A COMMON CELL BUFFER DEVICE 失效
公开(公告)号：JPH10247924A
公开(公告)日：1998-09-14
申请号：JP5129897
申请日：1997-03-06
申请人： FUJITSU LTD
发明人： KAWARAI KENICHI , KATO TSUGIO , MATSUOKA NAOKI , TOMONAGA HIROSHI , AMANO MITSUHARU
IPC分类号： H04Q3/00 , H04L12/28
摘要： PROBLEM TO BE SOLVED: To manage a network resource equally to each connection by controlling writing into a common cell sending the cells of plural connections on the terminal side of an ATM exchange to a network side. SOLUTION: The common cell FIFO buffer 1 of the ATM exchange for writing an inputted cell, reading according to a permitted sending rate by each connection and outputting to the network side is provided with a number of cells counter counting the number of cells at each connection within a common cell buffer 1 and a connection information managing table 2 to which the regulated value of the number of inputtable cells at each connection. A writing control part 11 monitors the number of cells counted value and the regulated value of the table 2 and decides the insertion of an incoming cell to a common cell buffer 1 and abolishment of the cell. Thereby, even when a transmission terminal dynamically varies a sending rate according to the state of the network, rate control can be realized to more connections without making each connection compete with each other.

5. 发明专利

JPH09162882A DISTRIBUTED CALL PROCESSING SYSTEM 失效
公开(公告)号：JPH09162882A
公开(公告)日：1997-06-20
申请号：JP31878995
申请日：1995-12-07
申请人： FUJITSU LTD
发明人： KAWARAI KENICHI , EZAKI YUTAKA , KATO TSUGIO
IPC分类号： H04Q3/00 , H04L12/28
摘要： PROBLEM TO BE SOLVED: To reduce processing requests for the processor of a central processing unit and to lighten exchange software by distributively arranging signaling processing parts and call reception control parts in respective line corresponding parts and setting a channel by making the line corresponding parts to be antonomous or making the central processing unit to take leadership. SOLUTION: In an ATM exchange 207 provided with the line corresponding parts 202 and 204, an ATM switch 203 and the central processing unit 206, the call reception control parts 208 judging whether resource quantity reported in a network can be secured or not for the setting request of connection from a terminal 201(a) are distributed and arranged in the line corresponding parts 202 and 204 of an output-side. In the system, the respective line corresponding parts 202 and 204 measure the number of passing cells and the call reception control parts 208 execute call reception control. Thus, the channel is set by making the line corresponding parts 202 and 204 to be antonomous and making the central processing unit 206 to take leadership with such constitution.

6. 发明专利

JP2005245034A Feedback control method and apparatus in atm exchange 有权
标题翻译： ATM交换机中的反馈控制方法和装置
公开(公告)号：JP2005245034A
公开(公告)日：2005-09-08
申请号：JP2005136291
申请日：2005-05-09
申请人： Fujitsu Ltd , 富士通株式会社
发明人： NAKAMICHI KOJI , SOMIYA TOSHIO , KAWASAKI TAKESHI , KAWARAI KENICHI , WATANABE NAOTOSHI , KUSAYANAGI MICHIO
IPC分类号： H04L12/813 , H04L12/827 , H04L12/911 , H04L12/56
摘要： PROBLEM TO BE SOLVED: To provide a specific ABR control function for realizing an ABR service in an ATM exchange system. SOLUTION: A subscriber line processing device 106 is provided with a function to calculate a cell to-and-fro delay time on the basis of a time from when a cell returns at a terminal till when it comes back. A switch section 101 or a multiple-separation device 108 is provided with a congestion detection function. A rate calculation means 104 calculates a transmission rate related to an exit-side line and writes into the cell, and a rate modification means 105 modifies the transmission rate properly according to the occurrence of the congestion. The rate modification means 105 also measures a number of communicating connections, in that situation, the number of the communicating connections expected to exist in a predetermined time is estimated with a predetermined means on the basis of the number of the communicating connections counted in a time shorter than the predetermined time. In addition, those estimated number of the communicating connections and actual number of the communicating connections determines a coefficient, and next estimation uses the coefficient to estimate more proper value. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于在ATM交换系统中实现ABR服务的特定ABR控制功能。解决方案：用户线处理装置106具有根据从终端到终端返回时间的时间计算一个一个一个一个的来回延迟时间的功能。开关部分101或多分离装置108具有拥堵检测功能。速率计算装置104计算与出口侧线相关的传输速率并写入小区，并且速率修改装置105根据拥塞的发生来适当地修改传输速率。速率修改装置105还测量多个通信连接，在这种情况下，预定时间内预期存在的通信连接的数量是以预定的方式根据在一段时间内计数的通信连接的数量来估计的比预定时间短。此外，这些通信连接的估计数量和通信连接的实际数量确定系数，并且下一个估计使用该系数来估计更适当的值。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

JP2002261826A INPUT LINE INTERFACE DEVICE AND PACKET COMMUNICATION DEVICE 失效
公开(公告)号：JP2002261826A
公开(公告)日：2002-09-13
申请号：JP2001060617
申请日：2001-03-05
申请人： FUJITSU LTD
发明人： KAWARAI KENICHI , NAGATA MASAKATSU , TOMONAGA HIROSHI , MATSUOKA NAOKI , KATO TSUGIO
IPC分类号： H04L12/951 , H04L12/46 , H04L12/773 , H04L12/775 , H04L12/953 , H04L29/00 , H04L12/56
摘要： PROBLEM TO BE SOLVED: To reduce a post-stage processing load for performing routing control by efficiently housing the packets of a high speed line. SOLUTION: A packet assigning means 11 divides variable length packets, and assigns and outputs those variable length packets to parallel lines. Flow group classifying means 12-1 to 12-n classify the packets into flow groups for each of the parallel lines. A sequence number applying means 13 applies sequence numbers to the packets corresponding to the flow groups or independently. Buffering means 14-1 to 14-n perform the buffer storage and reading of the packets applied with the sequence numbers, and controls the arrangement of the packets in the flow groups. A flow assignment switch 15 assigns and outputs the packets to each flow group.

8. 发明专利

JP2002077238A PACKET-SWITCHING DEVICE 失效
公开(公告)号：JP2002077238A
公开(公告)日：2002-03-15
申请号：JP2000262058
申请日：2000-08-31
申请人： FUJITSU LTD
发明人： TOMONAGA HIROSHI , NAGATA MASAKATSU , KAWARAI KENICHI , MATSUOKA NAOKI , OKABE KENICHI , URYU SHIRO
IPC分类号： H04L12/943 , H04L12/947 , H04Q11/04 , H04L12/56
摘要： PROBLEM TO BE SOLVED: To provide a packet-switching device, which reduces increase in hardware, when more packet switch devices are installed and which can prevent the overhead of a processing operation in a large-scale packet switching. SOLUTION: Rows of packets, which are input to the packet switch device from an input HW #0 to an input HW #3, are embedded in respective time slots A to D. The input packets are divided alternately in units of the time slots to be input to two 4×4 switches. In the 4×4 switches, ordinary switching operations are performed with their being divided into respective output ports. After the switching operations, the packets which come from the two 4×4 switches are multiplexed alternately to be output to an output WH #0 to an output HW #3. In this manner, by carry out the switching operations in units of packets, the overhead of the processing operations is suppressed, more packet switches can be installed easily, and the scale of the hardware can be suppressed to be small.

9. 发明专利

JP2001237844A PACKET INSERTION INTERVAL CONTROLLER AND PACKET INSERTION INTERVAL CONTROL METHOD 失效
公开(公告)号：JP2001237844A
公开(公告)日：2001-08-31
申请号：JP2000046451
申请日：2000-02-23
申请人： FUJITSU LTD
发明人： KAWARAI KENICHI , TERADA TAKESHI , ONO YASUHIRO , OBA YASUHIRO
IPC分类号： H04L12/70 , H04L12/801 , H04L12/815 , H04L12/911 , H04L12/951 , H04L12/28
摘要： PROBLEM TO BE SOLVED: To provide a packet insertion interval controller that can suppress increase in the hardware and flexibly cope with a change in the number of connections (the number of channels) for each communication system and in a cell insertion interval (packet insertion internal). SOLUTION: The packet insertion interval controller is provided with a count means (32) that has a 1st bit field to manage an insertion interval of a management packet requesting periodic insertion, a 2nd bit field to specify a logic path to send the management packet, and counting bits while periodically circulating the 1st bit field and the 2nd bit filed and with a control means (31) that specifies a logical path to transmit the management packet on the basis of the count denoted by the 2nd bit field of the count means and inserts the management packet to the specified logical path as its control when the count denoted by the 1st bit field of the count means is the prescribed value.

10. 发明专利

JP2001060967A PACKET SWITCH DEVICE 失效
公开(公告)号：JP2001060967A
公开(公告)日：2001-03-06
申请号：JP23559699
申请日：1999-08-23
申请人： FUJITSU LTD
发明人： TOMONAGA HIROSHI , MATSUOKA NAOKI , KAWARAI KENICHI , KATO TSUGIO
IPC分类号： H04L12/18 , H04L12/28 , H04L12/775 , H04L12/863 , H04L12/879 , H04L12/933 , H04L12/937 , H04L12/945 , H04L12/56
摘要： PROBLEM TO BE SOLVED: To reduce a memory amount by temporarily holding a plurality of fixed length packets, successively outputting them, dividing a memory address into fixed length blocks for the portion of the plurality of packets, managing an address by a block unit and giving an individual address in the block to every queue in the case of writing or reading. SOLUTION: In the case of writing, a writing address is issued by the writing block address and writing sequence number(SN) of a relevant logical output route queue to increase the writing SN. In the case of reading, a reading address is issued by the reading block address and reading sequence number(SN) of an applying logical output route queue to increase the reading SN. When the reading SN or the writing SN makes one round in the case of reading or writing, a succeeding block address is obtained. Thus, the capacity of an address management memory 12 is reduced to be one-tenth when one block is composed of 10 packets, for example.

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