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1. 发明专利

JPS51149726A METHOD OF CHECKING OBLIQUE MOVEMENT 失效
公开(公告)号：JPS51149726A
公开(公告)日：1976-12-22
申请号：JP7398875
申请日：1975-06-17
申请人： FUJITSU LTD
发明人： NAKATANI AKIO , FUJII KUNIO , KAKO NOBUYOSHI
IPC分类号： G06K13/063 , B65H7/10 , B65H7/14 , G06K13/067 , G06K13/07
摘要： PURPOSE:To detect oblique movement of cards when they are moving.

2. 发明专利

JPS62270067A FLOPPY DISK READING CONTROL SYSTEM 失效
公开(公告)号：JPS62270067A
公开(公告)日：1987-11-24
申请号：JP11554086
申请日：1986-05-19
申请人： FUJITSU LTD
发明人： KAKO NOBUYOSHI
IPC分类号： G11B20/10 , G11B19/02
摘要： PURPOSE:To attain the reliable adjustment by providing a central frequency setting circuit to select a voltage controlled oscillator group and set the central frequency of a variable frequency oscillator to an optimum value. CONSTITUTION:For a voltage controlled oscillator group (VCO group) 3, the capacity of a capacitor externally installed at a VCO is respectively different, each VCO oscillates a clock pulse with an inherent frequency and a frequency comes to be high from VCO No.1 to VCO No.n. A central frequency setting circuit 4 selects the central frequency of a clock pulse automatically by reading data from an FDD floppy disk for adjustment and a feeding-back signal from an initial setting VCO to a phase detecting device 21. Thus, the initial setting of the frequency is automatically selected and the reliable adjustment can be executed.

3. 发明专利

JPS5851366A CONTROL SYSTEM FOR FLOPPY DISK DEVICE 失效
公开(公告)号：JPS5851366A
公开(公告)日：1983-03-26
申请号：JP15101481
申请日：1981-09-24
申请人： FUJITSU LTD
发明人： IGUCHI HIROSHI , KAMIGAKI YOSHIHARU , KAKO NOBUYOSHI
IPC分类号： G06F3/06 , G11B19/12 , G11B20/10
摘要： PURPOSE:To perform processing while holding a format unchanged, and to perform an interchange of data by attaining access in >=2 kind of reading modes, discriminating the kind of the format, and controlling by a processing method which corresponds to the kind. CONSTITUTION:In sectors of respective cylinders in areas other than a cylinder 00 (index cylinder) each have an ID area 11 and a data area 12, and in the ID area, a cylinder number, a sector number, and record length are written. When formats of data on areas other than the index cylinder are read, there are 9 kinds of formats, so the reading is performed in a single-sided single-density (e.g., 128-1S) mode to discriminate the format. When the reading is still impossible, the mode is changed to the double-density mode. Thus, the modes are changed successively to discriminate the kind of the format on the basis of readable/unreadable results.

4. 发明专利

JPH03265037A LARGE CAPACITY MEMORY INITIAL DIAGNOSTIC CONTROL SYSTEM 失效
公开(公告)号：JPH03265037A
公开(公告)日：1991-11-26
申请号：JP6266190
申请日：1990-03-15
申请人： FUJITSU LTD
发明人： KAKO NOBUYOSHI
IPC分类号： G06F12/16 , G06F11/22
摘要： PURPOSE:To quickly execute the initial diagnosis at the time of start of the device by selecting simultaneously plural memory boards and executing the write and read-out of the same data, and comparing both data. CONSTITUTION:Usually, by an exclusive board selection signal line, each memory board is selected separately, respectively, but at the time of initial diagnosis, a common board selection signal line is activated, respective memory boards (1-1)-(1-n) are selected simultaneously, and the same data on a bus 3 are written simultaneously in each memory board. Subsequently, these data are read out of a memory and inputted to a data comparator 2 by output lines (6-1)-(6-n). The circuit 2 compares simultaneously each inputted data, and by outputting its propriety as a comparison checking output signal, and an initial diagnosis at the time of the start of a controller having a large capacity memory consisting of plural memory boards can be executed quickly.

5. 发明专利

JPS6232494B2 失效
公开(公告)号：JPS6232494B2
公开(公告)日：1987-07-15
申请号：JP15101581
申请日：1981-09-24
申请人： FUJITSU LTD
发明人： IGUCHI HIROSHI , TAKAHASHI TAKESHI , KAMIGAKI YOSHIHARU , KAKO NOBUYOSHI , INUYAMA SEIJI
IPC分类号： G06F13/10 , G06F3/06

6. 发明专利

JPS60128496A TRIMMING DATA OUTPUT UNIT 失效
公开(公告)号：JPS60128496A
公开(公告)日：1985-07-09
申请号：JP23681483
申请日：1983-12-15
申请人： FUJITSU LTD
发明人： SUGAWARA TOSHIROU , KAKO NOBUYOSHI
IPC分类号： G09G5/36 , G06T3/40 , G09G1/06 , H04N1/387

7. 发明专利

JPS5118600A 失效
公开(公告)号：JPS5118600A
公开(公告)日：1976-02-14
申请号：JP8984174
申请日：1974-08-07
申请人： FUJITSU LTD
发明人： SHIROYAMA ISAMU , NAKATANI AKIO , KAKO NOBUYOSHI
IPC分类号： B65H27/00 , G06K13/05 , G06K15/16

8. 发明专利

JPH02192078A VERIFYING CIRCUIT FOR FLOPPY WRITING DATA 失效
公开(公告)号：JPH02192078A
公开(公告)日：1990-07-27
申请号：JP1082089
申请日：1989-01-19
申请人： FUJITSU LTD
发明人： KAKO NOBUYOSHI
IPC分类号： G06F3/06 , G11B20/18
摘要： PURPOSE:To shorten the time needed for the verify of floppy writing data by reading data to be written to a floppy and comparing the data with writing data on a data bus. CONSTITUTION:Bit parallel data inputted from an input data bus are inputted to an FDC (Floppy Disk Control) circuit 1 and converted to the bit serial data for writing. Then, the data are written to a floppy medium 2. Here, the data just before the input to the medium 2 are fetched into a VFO circuit 3 and converted to the bit parallel data by a conversion circuit 4. The converted data are outputted to the output data bus. Then, the previously inputted data on the input data bus are compared with the data on the output data bus by a data collation circuit 5. Thus, since the data writing to the floppy medium 2 and the verify of the data are parallelly executed, the time needed for the verification of the floppy writing data can be shortened.

9. 发明专利

JPH01116815A CLOCK SWITCHING CIRCUIT 失效
公开(公告)号：JPH01116815A
公开(公告)日：1989-05-09
申请号：JP27631787
申请日：1987-10-30
申请人： FUJITSU LTD
发明人： KAKO NOBUYOSHI
IPC分类号： G06F1/04 , G06F1/06
摘要： PURPOSE:To prevent malfunction in clock switching by performing switching between an original clock signal and a clock signal, whose period is twice as long as the original clock signal, in accordance with polarity inversion of a clock signal having four-fold period of the original clock signal at the time of outputting a signal which instructs clock switching. CONSTITUTION:The clock signal switching operation by a multiplexer circuit 3 is performed when the clock switching instruction signal is given as '1'. This clock switching instruction signal is the output signal of a flip flop circuit 2, and the output signal is outputted when the clock switching signal inputted to the flip flop circuit 2 is '1' and polarity inversion (leading edge or trailing edge of the waveform) of the four-fold period clock signal is detected by a polarity inversion detecting circuit 4 and is given as a clock to the flip flop circuit 2. Consequently, it is unnecessary to stop the circuit operation or reset the circuit at the time of clock switching.

10. 发明专利

JPS63177240A CONTROL SYSTEM FOR MEMORY DIAGNOSIS 失效
公开(公告)号：JPS63177240A
公开(公告)日：1988-07-21
申请号：JP831187
申请日：1987-01-19
申请人： FUJITSU LTD
发明人： KAKO NOBUYOSHI
IPC分类号： G06F12/16
摘要： PURPOSE:To facilitate the memory diagnosis by using a bit rewriting register to hold a check bit to be given and reading out the check bits outputted from an error check collection circuit and said rewriting register and written into a memory circuit to use these check bits. CONSTITUTION:In a normal action mode an ECC circuit 1 produces a check bit for the data to be written into a memory 2 and writes the data 2-1 and the bit 2-2. When a check mechanism is diagnosed, a new check bit 2-2 to be written into the memory 2 is previously stored in a check bit writing register 3 via a CPU. Then the circuit 1 reads out those data 2-1 and bit 2-2 to carry out a checking task. Then a pseudo memory error generating signal obtained later is read out by the CPU for execution of the diagnosis of a memory check function.

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