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1. 发明专利

JP2015049404A 光導波路基板及び情報処理装置有权
标题翻译：光波导基板和信息处理器
公开(公告)号：JP2015049404A
公开(公告)日：2015-03-16
申请号：JP2013181621
申请日：2013-09-02
申请人：富士通株式会社 , Fujitsu Ltd
发明人： USUI DAISUKE , NAGARA KOHEI , IWAMA MASAYASU
IPC分类号： G02B6/30 , G02B6/42
CPC分类号： H04B10/2504 , G02B6/421 , G02B6/4214 , G02B6/43
摘要：【課題】データ伝送を行う光導波路と光素子との間の光軸調整を適切に行うことを課題とする。【解決手段】光導波路基板は、光導波路が形成された基板本体と、前記光導波路と対向配置される入射部又は出射部を備えるとともに、外周部に第1の磁気部が設けられた信号ケーブルが収容されるケーブル収容穴が設けられたケーブル保持部と、前記ケーブル収容穴の内周壁に設けられ、前記第1の磁気部との間で斥力を発生する第2の磁気部と、を備える。第1の磁気部と第2の磁気部との間に生じる斥力によって自律的に信号ケーブルの光軸調整が行われる。【選択図】図8
摘要翻译：要解决的问题：在光波导与在其间传送数据的光学元件之间进行适当的光轴调节。解决方案：一种光波导基板，包括：形成有光波导的基板; 包括入射部分或与光波导相对布置的发射部分的电缆保持部分和用于容纳包括设置在外周上的第一磁性部分的信号电缆的电缆容纳孔; 以及设置在电缆容纳孔的内周壁上的第二磁性部分，并且在第一磁性部分和第二磁性部分之间产生排斥力。在第一磁性部分和第二磁性部分之间产生的排斥力执行信号电缆的自主光轴调节。

2. 发明专利

JPH05183895A REFRESHING CONTROL CIRCUIT 失效
公开(公告)号：JPH05183895A
公开(公告)日：1993-07-23
申请号：JP34642991
申请日：1991-12-27
申请人： FUJITSU LTD
发明人： IWAMA MASAYASU , FUKUI HIROKAZU , ITO AKIRA , MIYAKE HIROSHI , SAKAI KIYOSHI
IPC分类号： H04N1/41 , G06T1/20 , G06T9/00 , H04N19/102 , H04N19/107 , H04N19/174 , H04N19/196 , H04N19/42 , H04N19/50 , H04N19/503 , H04N19/65 , H04N19/67
摘要： PURPOSE:To realize a refreshing control circuit in circuit construction capable of easy LSI. CONSTITUTION:Predicted image data and '0' block data are selectively selected and outputted by a selector part 11, and the selector part 11 receives the number of counted blocks from a single screen block counter part 13 with its decoder part 12 and each time the received counted number coincides with a decoded value, outputs '0' block data. Then a shifting control counter part 14 gives the counter part 13 a load value which controls the single screen block counter 13 to shift the number of counted blocks by one each time one screen is updated.

3. 发明专利

JPH04129342A PHASE ADJUSTMENT SYSTEM 失效
公开(公告)号：JPH04129342A
公开(公告)日：1992-04-30
申请号：JP24877790
申请日：1990-09-20
申请人： FUJITSU LTD
发明人： IWAMA MASAYASU
IPC分类号： H04J3/06 , H04L7/00
摘要： PURPOSE:To realize the phase adjustment system for synchronizing frames of plural data having a different input timing with a small circuit scale. CONSTITUTION:The system is provided with a memory section comprising (n-1) memories with respect to n-channels of data inputs. The order of input of a reset signal synchronized at a head to a data of n-channel, a data of (n-1) channels in an early timing is selected and inputted to a memory section in response to the result of discrimination, a data of one channel in a slowest timing is inputted to a data select section and a data write address with respect to the memory section is generated by starting the count in response to the result of discrimination of the input order to write the data. Moreover, the input of a reset signal at a slowest time is discriminated and the count is started in response to the result of discrimination to generate a read address to the memory section and to read the data from the memory section, and the output location at n-channel data output is decided for the data read from the memory section in response to the input order to be discriminated and for the data of one channel selected by the memory select section to generate an output.

4. 发明专利

JPH03269662A HIGH SPEED MEMORY ACCESS SYSTEM 失效
公开(公告)号：JPH03269662A
公开(公告)日：1991-12-02
申请号：JP6806290
申请日：1990-03-20
申请人： FUJITSU LTD
发明人： IWAMA MASAYASU , ITO AKIRA
IPC分类号： G06F12/06 , G06F13/38
摘要： PURPOSE:To omit a zero address register and to reduce the circuit scale by controlling the switch of input data in accordance with the information on a memory under designation of a writing operation, an input/output memory selection signal, and an input/output data reset signal respectively. CONSTITUTION:An input data separator means 3 divides the input data into the even data and the odd data. These separated data are inputted to the memories 1 and 2 with switching and also read alternately from both memories 1 and 2. In this case, the input/output data switch control means 6 and 7 decides whether the input/output data switching should be carried out or not to both memories based on the information showing the memory under designation of a writing operation, an input/output memory selection signal, and an input/ output data reset signal. Thus the input/output data are switched to both memories 1 and 2. In such a constitution, a zero address register is omitted and the circuit scale is reduced.

5. 发明专利

JP2006344680A IC PACKAGE, ITS MANUFACTURING METHOD, AND INTEGRATED CIRCUIT DEVICE 审中-公开
公开(公告)号：JP2006344680A
公开(公告)日：2006-12-21
申请号：JP2005167281
申请日：2005-06-07
申请人： FUJITSU LTD
发明人： IWAMA MASAYASU
IPC分类号： H01L23/12 , H01L23/00
摘要： PROBLEM TO BE SOLVED: To provide an improvement in heat dissipation characteristics and enhancement in proof strength against the variation of potential of power supply or ground caused by simultaneous switching by the side of an IC chip with respect to a package of integrated circuits. SOLUTION: An IC package 10 is provided with a substrate 6 in which an IC chip 4 is mounted, and a covering section 8 for covering the IC chip mounted in the substrate. In either or both sides of the substrate or the covering section, it has single or a plurality of laminated power supply layers 21, 22, 23, 24 and 25, and ground layers 31, 32, 33, 34, 35 and 36. It comprises single or a plurality of built-in capacitors C1-C9 by arranging oppositely and sandwiching high dielectric layers 41-49 between the power supply layer and the ground layer. Further, an IC package is constituted such that an inner side conductor layer 35 contacted with an IC chip and an outside conductor layer 36 are connected by intervening thermal vias 101-106 and 111-116. It is also provided with covering conductors 131-13n. COPYRIGHT: (C)2007,JPO&INPIT

6. 发明专利

JPH08190436A POWER SOURCE CONTROL CIRCUIT 失效
公开(公告)号：JPH08190436A
公开(公告)日：1996-07-23
申请号：JP304795
申请日：1995-01-12
申请人： FUJITSU LTD
发明人： IWAMA MASAYASU
IPC分类号： H02J1/00 , G05F1/56
摘要： PURPOSE: To prevent variation in power line by providing a feedback control circuit which monitors and compares the voltage value of the power line with a reference voltage and provides feedback to the power line so that the power line has a constant value. CONSTITUTION: An operational amplifier 10 as the feedback control circuit operates by the power source of a system different from a +5V line. An output buffer 5 operates at the same time and when a current is supplied from the +5V power source, the voltage of the power line 6 drops, so that the operational amplifier 10 detects the voltage drop of the power line 6. In concrete, the voltage of the power line 6 is compared with the reference voltage +5V. The operational amplifier 10 supplies a current to the power line 6 according to the difference between the reference voltage +5V and the voltage of the power line 6 to compensate the voltage drop of the power line 6. Consequently, the voltage of the power line 6 is controlled to be equal to the reference voltage +5V, and the output buffer 5 operates to suppress the voltage drop of the power line 6.

7. 发明专利

JPH05244582A 失效
公开(公告)号：JPH05244582A
公开(公告)日：1993-09-21
申请号：JP4293692
申请日：1992-02-28
申请人： FUJITSU LTD
发明人： IWAMA MASAYASU
IPC分类号： H04N19/50 , H04N19/503 , H04N19/65 , H04N19/85 , H04N7/137
摘要： PURPOSE:To realize the random refresh control signal generating circuit in which a refreshed block is made unremarkable with respect to the random refresh control signal generating circuit where one pattern is divided equally into 1/n and each 1/n of the pattern is refreshed at random in the picture processing. CONSTITUTION:This circuit is provided with an n-adic pattern counter 10 counting number corresponding to (n) being 1/n equal division of a pattern, a random pattern generating circuit 20 generating random pictures of 1-M, a constant number generating circuit 30 generating a constant '(n-M+1)-n', a decoder 40 generating a signal inhibiting the operation of the random pattern generating circuit 20 at a prescribed count and a signal selecting one of constants generated by the constant number generating circuit 30, and a selection circuit 50 receiving an output of the random pattern generating circuit 20 and an output of the constant number generating circuit 30.

8. 发明专利

JPH0595482A DEAD ZONE CONTROL CIRCUIT 失效
公开(公告)号：JPH0595482A
公开(公告)日：1993-04-16
申请号：JP25556091
申请日：1991-10-02
申请人： FUJITSU LTD
发明人： IWAMA MASAYASU , FUKUI HIROKAZU , ITO AKIRA , TSUBAMOTO HIROTA , SAKAI KIYOSHI
IPC分类号： H03M1/12 , G06T9/00 , H04N1/41 , H04N7/30
摘要： PURPOSE:To facilitate large scale circuit integration by controlling data with logic elements only, to eliminate the need for intervention of software processing and to attain real time processing. CONSTITUTION:Coefficient data D obtained by quantizing block data comprising plural picture element data are sequentially inputted to the control circuit. Each of detection sections 20, 21 detecting 0 and 1 respectively detects data corresponding to 0 and 1 respectively and when outputs 0out from the 0 detection section 20 are consecutive for a prescribed number of times, a consecutive 0 detection section 22 sends a C0 signal to a data conversion section 23. The conversion section 23 receiving the signal rewrites received coefficient data into 0 coefficient data D' selectively only when a 1 detection output 1out appears after the C0 signal and in other cases, the section 23 outputs the coefficient data as they are as D'. Thus, the dead zone is controlled by employing only logic elements, the large scale circuit integration is facilitated and real time processing is attained.

9. 发明专利

JPH0540776A TWO-DIMENSIONAL DCT MATRIX OPERATION CIRCUIT 失效
公开(公告)号：JPH0540776A
公开(公告)日：1993-02-19
申请号：JP19383891
申请日：1991-08-02
申请人： FUJITSU LTD
发明人： IWAMA MASAYASU
IPC分类号： H04N1/41 , G06F17/14 , H04N7/30
摘要： PURPOSE:To realize a DCT (discrete cosine transform) matrix operation circuit which pan reduce the circuit scale for two-dimensional DCT matrix operation. CONSTITUTION:An output consisting of a matrix where elements of rows and those of columns of an input matrix are exchanged in a transposing RAM 2 is generated to a one-dimensional DCT matrix operation circuit 1, and an input signal and the output of the transposing RAM 2 are switched by a selector 3 and are inputted to the DCT matrix operation circuit l. The DCT matrix obtained by one-dimensional DCT matrix operation of the input signal is subjected to one-dimensional DCT matrix operation again with respect to the DCT matrix obtained by exchanging elements of rows and those of columns, thereby obtaining a two-dimensional DCT matrix.

10. 发明专利

JPH04326138A HIGH-SPEED MEMORY IC 失效
公开(公告)号：JPH04326138A
公开(公告)日：1992-11-16
申请号：JP12185391
申请日：1991-04-25
申请人： FUJITSU LTD
发明人： IWAMA MASAYASU , ITO AKIRA
IPC分类号： G06F12/04 , G11C11/401
摘要： PURPOSE:To provide the high-speed memory IC which can be read at a high speed. CONSTITUTION:The memory IC is provided with a serial-parallel conversion shift register part 1 and converts a serial data input into (n)-bit parallel data and a parallel data latch part 2 is provided to hold the parallel data output of the serial-parallel conversion shift register part 1 for an (n)-bit period respectively. A storage part 3 is provided to write the data, held in the parallel data latch part 2, by (n) bits in parallel, and the data are read out by (n) bits in parallel; and a parallel-serial conversion shift register part 4 is provided to shift the data read out of the storage part 3 in parallel at each (n)-bit period in order, thereby generating a serial data output.

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