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1. 发明专利

JPH0411787A SEMICONDUCTOR LIGHT RECEIVING DEVICE 失效
公开(公告)号：JPH0411787A
公开(公告)日：1992-01-16
申请号：JP11232090
申请日：1990-04-28
申请人： FUJITSU LTD
发明人： INOUE KOICHI
IPC分类号： H01L31/10
摘要： PURPOSE:To enhance a yield and to prevent a decrease in a quantum efficiency by forming an insulator and a multilayer film reflector of semiconductor on a semiconductor substrate, and reflecting a light in a direction of a light absorption layer. CONSTITUTION:A semiconductor substrate 2 has a pair of main surfaces 3, 4, a light receiving surface 5 formed on one surface 3, and a light absorption layer 1 formed therein. When a light hpsi incident on the surface 5 is not absorbed to the layer 1, but arrived at the other surface 4, a multilayer film reflector 6 reflects the light toward the layer 1. The reflector 6 is formed by alternately laminating an insulator layer 7 and a semiconductor layer 8 on the surface 4 of the substrate 2. Thus, the layer 1 improves to absorb the light, its yield is improved, and a decrease in a quantity efficiency can be prevented.

2. 发明专利

JPH0380733A DATA TRANSFER SYSTEM 失效
公开(公告)号：JPH0380733A
公开(公告)日：1991-04-05
申请号：JP21774189
申请日：1989-08-24
申请人： FUJITSU LTD
发明人： INOUE KOICHI
IPC分类号： G06F15/16 , G06F13/38 , G06F15/177 , H04L12/40
摘要： PURPOSE:To selectively transmit data to processors of one set or plural sets by setting ion advance plural discrimination codes, and designating one of discrimination code (cell ID) peculiar to each processor, and a discrimination code (group ID) including plural sets all together. CONSTITUTION:To plural pieces of processors (0)-1 for constituting a multiprocessor system, a first discrimination code peculiar to each processor, and a second discrimination code when includes plural sets all together and given newly are given in advance, and when the processor 1 of a transmitting side transmits a packet, the processor 1 of a receiving side is designated by a first receiving destination discrimination code or a second receiving destination discrimination code contained in the packet concerned, and the processor 1 of the receiving side concerned compares the first receiving destination discrimination code or second receiving destination discrimination code, and the first discrimination code or second discrimination code held in each processor 1, and receives the packet concerned in accordance with the respective comparison results.

3. 发明专利

JPH0376274A SEMICONDUCTOR PHOTODETECTIVE ELEMENT 失效
公开(公告)号：JPH0376274A
公开(公告)日：1991-04-02
申请号：JP21348089
申请日：1989-08-18
申请人： FUJITSU LTD
发明人： OGAWA ISAO , KAGAWA SHUZO , INOUE KOICHI
IPC分类号： H01L31/10
摘要： PURPOSE:To decrease an electrode in contact resistance and to improve it in adhesion by a method wherein an electrode layer is formed through the intermediary of a contact.cover layer which is in contact with a P layer covering it. CONSTITUTION:An InGaAs layer 30 is formed to fill the whole contact hole of a coating film 22 covering a P-type diffusion region 18. That is, the InGaAs layer 30 is made to function as a contact layer which makes the contact resistance between an electrode and the P-type diffusion region 18 small and concurrently to serve as a cover layer which covers the P-type diffusion region 18 or as a contact.cover layer 30. By this setup, Ti contained in an electrode 24 is prevented from coming into direct contact with InP contained in the P-type diffusion region 18, so that the electrode 24 can be improved in adhesion.

4. 发明专利

JPH0322719A DATA COMMUNICATION EQUIPMENT FOR MOBILE RADIO 失效
公开(公告)号：JPH0322719A
公开(公告)日：1991-01-31
申请号：JP15707489
申请日：1989-06-20
申请人： TOSHIBA CORP , FUJITSU LTD , MITSUBISHI ELECTRIC CORP , MATSUSHITA ELECTRIC IND CO LTD
发明人： TSUKUI YASUHIRO , HANAWA TETSUYA , TAKEGAKI HIROSHI , INOUE KOICHI
IPC分类号： H04B7/26
摘要： PURPOSE:To prevent a battery from being wasted by stopping an acquisition scan for an idle signal for a specific time unless the idle signal is acquired even for a specific time after the acquisition scan is made over plural control channels, and restarting it a specific time later or when a request to send is made. CONSTITUTION:Timers 20 and 21 are added in addition to a timer 17. The timer 20 detects no idle signal being detected even for the specific time after the acquisition scan for the idle signal is made over plural control channels. The acquisition scan is halted through the timer 21 for the specific time unless the idle signal is acquired, and restarted the specific time later or when the request to send is generated. Consequently, the waste of the battery as a power source for operation can be suppressed.

5. 发明专利

JPH0322718A DATA COMMUNICATION EQUIPMENT FOR MOBILE RADIO 失效
公开(公告)号：JPH0322718A
公开(公告)日：1991-01-31
申请号：JP15707389
申请日：1989-06-20
申请人： TOSHIBA CORP , FUJITSU LTD , MITSUBISHI ELECTRIC CORP , MATSUSHITA ELECTRIC IND CO LTD
发明人： OBA RYOHEI , TSUKUI YASUHIRO , HANAWA TETSUYA , TAKEGAKI HIROSHI , INOUE KOICHI
IPC分类号： H04B7/26
摘要： PURPOSE:To acquire a control channel which is high in use frequency immediately by acquiring only a control channel specified with the storage contents of a memory card. CONSTITUTION:The memory card 23 is stored with the numbers of control channels that a user uses normally according to priority. This memory card 23 is inserted into the read slot of a reader to read its storage contents, which are written on a memory 20. Then a central control unit 18 acquires and scans the control channels corresponding to the control channel numbers stored on the memory card 23 according to the specified priority. Consequently, the control channel which is high in use frequency can be acquired immediately.

6. 发明专利

JPH01283664A DATA TRANSFER SYSTEM IN PAPALLEL COMPUTERS 失效
公开(公告)号：JPH01283664A
公开(公告)日：1989-11-15
申请号：JP11421088
申请日：1988-05-11
申请人： FUJITSU LTD
发明人： IKESAKA MORIO , INOUE KOICHI
IPC分类号： G06F15/17 , G06F13/38 , G06F15/16
摘要： PURPOSE:To eliminate a useless input processing in other processor than a transmitting destination by dividing a header reception processing and a data reception processing, and disconnecting a data bus by a processor which has known that it is not the transmitting destination by a header reception, so that the data reception processing is not executed. CONSTITUTION:Since a reception processing of a header and a reception processing of data are divided, a head reception end notice register 21 is provided as each PE (processing element) 2, and a header reception end instructing register 11 is provided as a transmitting mechanism. In this state, an output of each header reception end notice register 21 is brought to wired connection and inputted to the header reception end instructing register 11, so that AND of each header reception end notice register 21 is set. As for the receiving PE 2, the PE which has been a transmitting destination sets the header reception end notice register 21, and the PE which has not been the transmitting destination disconnects a bus by a bus control means 23 and sets the header reception end notice register 21 and a data reception end notice register 22. In such a way, the operation rate of the PE can be improved by eliminating a useless input processing in the receiving PE.

7. 发明专利

JPS63143661A DATA TRANSFER CONTROL SYSTEM IN MULTIPROCESSOR SYSTEM 失效
公开(公告)号：JPS63143661A
公开(公告)日：1988-06-15
申请号：JP29005386
申请日：1986-12-05
申请人： FUJITSU LTD
发明人： IKESAKA MORIO , INOUE KOICHI
IPC分类号： G06F15/16 , G06F15/163 , G06F15/177
摘要： PURPOSE:To prevent the reduction of transfer capacity and the generation of a transfer stop state or the like by restricting the sending of a data packet when the difference between the count values of counting means indicates a value smaller than the contents of a block residual limiting register. CONSTITUTION:The titled system is provided with a counting means 17 for counting the number of data packets accumulated in the storage block of an input/output buffer 12 in a transfer control circuit (TC) 5 in each unit processor (UP) and waiting for being sent in each input/output terminal to be sent and a counting means 16 for counting the number of unused idle storage blocks. In addition, a block number ratio limiting register 18 or a block residual limiting number register 19 to be set up by a CP (processor for executing random processing under control based upon a program) 4 is prepared and always monitored by the CP 4 and an input/output control circuit 11. When the using rate of the input/output buffer 12 is increased, the sending of data packets is restricted. Consequently, excess data sending can be suppressed.

8. 发明专利

JPS62263563A NETWORK CONSTITUTION SYSTEM 失效
公开(公告)号：JPS62263563A
公开(公告)日：1987-11-16
申请号：JP10611286
申请日：1986-05-09
申请人： FUJITSU LTD
发明人： ISHIHATA HIROAKI , KAKIMOTO MASANORI , INOUE KOICHI
IPC分类号： G06F15/80 , G06F15/16 , G06F15/173
摘要： PURPOSE:To dynamically change the constitution of a network constituted of a multiprocessor by providing a switch circuit for outputting information inputted from an optional communication port (reception part) to an optional communication port (transmission part) to form a by-pass communication path. CONSTITUTION:In the multiprocessor system consisting of plural cells, the switch circuit 3 for outputting the input information from the optional communication port (reception part) 2 to the optional communication port (transmission part) 1 and a switch control register 31 for controlling this switch circuit 3 are provided, specific control data is applied to the switch control register circuit 31 to form the optional by-pass communication pass and the the network constituting the multiprocessor system is dynamically changed. Thereby, the switch circuit provided every cell and constituting the multiprocessor system is only energized to dynamically change the constitution of the network.

9. 发明专利

JPS61264833A DATA TRANSFER AND CONTROL SYSTEM 失效
公开(公告)号：JPS61264833A
公开(公告)日：1986-11-22
申请号：JP10655185
申请日：1985-05-18
申请人： FUJITSU LTD
发明人： INOUE KOICHI , SATO KEIJI , IKESAKA MORIO
IPC分类号： G06F13/00 , G06F15/16 , G06F15/163 , H04L12/00
摘要： PURPOSE:To attain efficient data transfer by providing a bit pattern field representing a destination node to a transfer packet and using a bit pattern so as to designate a reception node thereby designating the destination nodes of an optional combination. CONSTITUTION:A data inputted to an input terminal 21 is inputted to a shift register 22 and shifted synchronously with a clock. On the other hand, the data is inputted to a detector 23 to detect the head of a packet and a comparator 28 is made enable with a delay by a destination node designation field length by a delay device 25. A value for sending end detection, all 1 is stored in a comparison value register 27 and the comparator 28 compares the said value with the content of the register 22. When the are equal, an FF 29 is set and the sending of a new packet is indicated and in case of reset, the transfer of the input data as it is indicated. The transfer data of the new packet is loaded to a shift register 31 and outputted to a link via an AND circuit 33, an OR circuit 34 and a buffer 35.

10. 发明专利

JPS61206048A RISING SYSTEM FOR DATA PROCESSING SYSTEM 失效
公开(公告)号：JPS61206048A
公开(公告)日：1986-09-12
申请号：JP4794885
申请日：1985-03-11
申请人： FUJITSU LTD
发明人： INOUE KOICHI , SATO KEIJI , IKESAKA MORIO
IPC分类号： G06F11/22 , G06F1/00 , G06F15/16 , G06F15/177
摘要： PURPOSE:To prevent that cutting and dividing are executed from a system at the time of the defect and the system as whole is immediately down by providing the action checking device and the device to connect and cut away with the status bus at respective processors. CONSTITUTION:There are processors 21-24, a host processor judges the information of a status bus 33 and checks successively a processor. The host processor gives a checking starting signal and a suitable time passes, and thereafter, the satisfactory status does not return or the abnormality is found at the time of checking the status itself, and then, for the processor, a cutting-away instruction line 34-2 is temporarily made into 0, and an FF 63 is cut away from the bus 33 through logical arithmetic circuits 72, 73, FF 61 and 62 and a logical element 64. After all processors are checked, the action rise of the system is executed by the resetting line 34-3. The processor, which is judged to defective by checking until then, is cut away, does not record the unfair information in the status bus since the status bus is cut away.

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