专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPS5942598A Rule synthesization/connection circuit 失效
标题翻译：规则合成/连接电路
公开(公告)号：JPS5942598A
公开(公告)日：1984-03-09
申请号：JP15357182
申请日：1982-09-03
申请人： Nippon Telegraph & Telephone , Fujitsu Ltd
发明人： INDOU KIYOSHI , ISHIKAWA KOUICHIROU , MURAKAMI NORIYA , HASHIMOTO SHIYUUICHI , TAKENO MINORU
IPC分类号： G10L13/06

2. 发明专利

JPS5856181A INTERPOLATION ARITHMETIC CIRCUIT 失效
公开(公告)号：JPS5856181A
公开(公告)日：1983-04-02
申请号：JP15552481
申请日：1981-09-30
申请人： FUJITSU LTD
发明人： HASHIMOTO SHIYUUICHI , YASUI YUTAKA , TAKENO MINORU
IPC分类号： G06F17/17 , G06F15/353
摘要： PURPOSE:To prevent an error in interpolation by adding 1 to an interpolation value at specified intervals and at a frequency which corresponds to the size of data to be monitored by a correcting circuit. CONSTITUTION:Two successive data FD are inputted and the preceding data is subtracted from the trailing data at a part SUB to obtain their difference data, which is divided at a part SE by the number of sampling periods during one frame period. Then, the division result is added successively at a part AD1 to the precedent data at every sampling period to obtain an interpolation value successively. Then, data consisting of the low-order bit group of the difference data cut-off in the division is monitored by a correcting circuit CP, and ''1'' is added to the successively obtained interpolation value by the correcting circuit CP at specified intervals and at a frequency which corresponds to the size of said monitored data, thereby correcting an error in interpolation.

3. 发明专利

JPS59225448A DIVISION ARITHMETIC CIRCUIT 失效
公开(公告)号：JPS59225448A
公开(公告)日：1984-12-18
申请号：JP10126983
申请日：1983-06-06
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKENO MINORU , HASHIMOTO SHIYUUICHI , INDOU KIYOSHI , ISHIKAWA KOUICHIROU
IPC分类号： G06F7/537 , G06F7/52 , G06F7/535
摘要： PURPOSE:To simplify the constitution of hardware and also to improve an arithmetic speed by comparing a divided or a partial remainder and a divisor at a magnitude comparator circuit, and proceeding the processing from the result. CONSTITUTION:A divided register AR, divisor resiter BR and a quotient register CR storing respectively a divided, divisor and a quotient are constituted respectively as a two-way register. The magnitude comparator circuit COMP compares the content of the dividend register AR and the divisor register BR, the content of the divisor register BR is subtracted from the content of the dividend register AR from the result of comparison and the result of subtraction is returned to the dividend register AR. A timing control circuit TC controls that the content of the dividend register AR and the divisor register BR are compared sequentially by the magnitude comparator circuit COMP and transmits an output of the magnitude comparator circuit COMP to the quotient register CR and stores the result in it.

4. 发明专利

JPS55133594A METHOD OF LONGITUDINALLY CONNECTING DIP TYPE ELECTRONIC PARTS 失效
公开(公告)号：JPS55133594A
公开(公告)日：1980-10-17
申请号：JP4102479
申请日：1979-04-06
申请人： FUJITSU LTD
发明人： YOSHINO HARUYUKI , KANEMOTO TSUTOMU , TAKANO SHIGERU , HASHIMOTO SHIYUUICHI
IPC分类号： H05K3/32 , H01L23/32

5. 发明专利

JPS5431239A SIGNAL TRANSMISSION SYSTEM FOR BUS TRANSMISSION LINE 失效
公开(公告)号：JPS5431239A
公开(公告)日：1979-03-08
申请号：JP9729877
申请日：1977-08-13
申请人： FUJITSU LTD
发明人： MATSUNAGA HIROSHI , OBARA SHINICHIROU , TAKANO SHIGERU , HASHIMOTO SHIYUUICHI
IPC分类号： H04L25/02 , G06F3/00 , G06F17/40 , H04B3/50
摘要： PURPOSE:To eliminate the noise caused by the earth potential difference through the electric isolation between the bus transmission line and the transmission and reception circuits of each transmitter and receiver by providing the optical coupling element.

6. 发明专利

JPS60162960A SETTING SYSTEM FOR DELAY CLOCK 失效
公开(公告)号：JPS60162960A
公开(公告)日：1985-08-24
申请号：JP1881384
申请日：1984-02-02
申请人： FUJITSU LTD
发明人： HASHIMOTO SHIYUUICHI
IPC分类号： G01R13/28 , G01R13/20 , G06F1/04 , H03K23/58 , H03K23/66
摘要： PURPOSE:To increase a delay interval by providing separately a delay clock which has a longer period than a sampling clock. CONSTITUTION:When an FF circuit F turns on, a counting circuit CNT2 added separately is enabled as well as an original counting circuit CNT1. Consequently, the circuit CNT1 starts counting the clock CLOCK2 at the same time. An operator sets the number of delay clocks to terminals D0-Dn of the circuit CNT2 as well as the circuit CNT2 before measuring operation, and the circuit CNT2 generates an output signal when its counted value attains to the set number of delay clocks. A clock CLOCK2 is generated by dividing the frequency of a clock CLOCK1, so the output of the circuit CNT2 and the output signal of the circuit CNT1 are generated at the same time. Therefore, they are ANDed by an AND gate G to obtain a memory write end signal. Further, the circuit CNT1 continues to count until the circuit CNT2 finishes counting. Consequently, a delay time is increased without decreasing sampling density.

7. 发明专利

JPS5416991A DRIVING CIRCUIT OF LIGHT EMITTING DIODES BY CML ELEMENTS 失效
公开(公告)号：JPS5416991A
公开(公告)日：1979-02-07
申请号：JP8158377
申请日：1977-07-08
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD
发明人： HASHIMOTO SHIYUUICHI , IWASA KIYOUICHI , HORINO NAOHARU , TOKURA TAKASHI , OKAMURA KAZUMASA
IPC分类号： H01L33/00 , H05B33/08 , H05B37/02
摘要： PURPOSE:To obtain a driving circuit of light emitting diodes by CML elements without requiring any special power source other than CML system power source by enabling flickering of the light emitting diode to be performed positively by shifting the output level of the CML element.

8. 发明专利

JPS60103723A CLOCK INTERRUPTION DETECTING CIRCUIT 失效
公开(公告)号：JPS60103723A
公开(公告)日：1985-06-08
申请号：JP21120583
申请日：1983-11-10
申请人： FUJITSU LTD
发明人： HASHIMOTO SHIYUUICHI
IPC分类号： H03K5/19 , G06F1/04
摘要： PURPOSE:To output a clock disconnection signal for the period of a clock pulse number during disconnecting period by constituting the circuit with a monostable multivibrator, a delay circuit, an AND circuit and a set/reset flip-flop and using an output of the flip-flop as the clock disconnection signal. CONSTITUTION:The monostable multivibrator OM is constituted by connecting a capacitor CM and a resistor RM to terminals C, R. Since an output signal 5 is extacted from a terminal MQ', the signal is an inverting signal of an output signal 3 at a terminal MQ. The output signal 5, a signal 6 delaying the output signal 3 at the terminal MQ by a delay circuit DL and a clock signal 1 are inputted to the NAND gate NA. An output signal 7 and the clock signal 1 of the NAND gate NA are fed respectively to terminals S and R of a set/reset flip-flop SRF, the clock disconnection signal 8 is outputted from a terminal SRQ so as to display clock disconnection.

9. 发明专利

JPS59231647A HOLDING TYPE REGISTER ACCESS SYSTEM 失效
公开(公告)号：JPS59231647A
公开(公告)日：1984-12-26
申请号：JP10713883
申请日：1983-06-15
申请人： FUJITSU LTD
发明人： HASHIMOTO SHIYUUICHI
IPC分类号： G06F5/06 , G06F13/38 , G06F13/40
摘要： PURPOSE:To extract repeatedly data by providing a tri-state buffer and specifying a single address through a data receiving bus. CONSTITUTION:One-word data d1-dn from a data transmitting bus 1 are transmitted to holding type registers 5-1-5-n together with respective fed addresses a1-an and n-word data d1-dn are stored in the registers 5-1-5-n. In this state, when only one kind of address (a) and a data extraction indication supplied from the data receiving bus 2 to the registers 5-1-5-n in common are sent out once, an access signal C drives the counting circuit CNT in a control part 6 once to output logic 1 from a terminal Q0 and logic 0 from terminals Q1-Qm. Consequently, a decoder DCR outputs an enable signal en1 from a terminal 01 to energize a tri- state buffer 7-1. Then, the register 5-1 is connected to the data receiving bus 2 to allow the stored data d1 to be extracted. Similarly, data are extracted successively up to the holding type register 5-n.

10. 发明专利

JPS57123716A Digital filter 失效
标题翻译：数字滤波器
公开(公告)号：JPS57123716A
公开(公告)日：1982-08-02
申请号：JP864681
申请日：1981-01-23
申请人： Fujitsu Ltd , Nippon Telegr & Teleph Corp
发明人： HASHIMOTO SHIYUUICHI , YASUI YUTAKA , ITAKURA FUMITADA , SAGAYAMA SHIGEKI
IPC分类号： H03H17/02 , H03H17/04
CPC分类号： H03H17/0461
摘要： PURPOSE:To eliminate the influence of an overflow by constituting a multiplier which performs continuous arithmetic regarding only significant data length without any excessive bit, and inserting 0 into the contents of a register in accordance with the number of parameters on detecting an overflow of the arithmetic result. CONSTITUTION:A digital filter consists of a multiplier MPL, an adder (+), a subtracter (-), delay registers DR1-DR3, a partialsum register REG, and a register ZR, and performs digital arithmetic processing on pipeline basis. The MPL is constituted by cascading an initial-stage module, a basic module, a discarding module, and a final-stage module, and performs continuous arithmetic regarding only significant data length without any excessive bit. A control circuit DCNT when detecting an overflow of the arithmetic result at the final stage of an arithmetic loop sends 0 to close gates G1-G6, thereby inserting the 0 into the DR1-DR3 only in a period which corresponds to parameters. The coefficients F of the MPL are inputted successively on time-division mode, and an input L(t) and timing are adjusted by the register ZR, thereby sending an output W(t) from a gate G3 synchronously with an output synchronizing signal SYN.
摘要翻译：目的：通过构成一个乘法器来消除溢出的影响，该乘法器只对有效的数据长度进行连续运算而没有任何过多的位，并根据检测到算术溢出的参数数将0插入到寄存器的内容中结果。构成：数字滤波器由乘法器MPL，加法器（+），减法器（ - ），延迟寄存器DR1-DR3，偏置寄存器REG和寄存器ZR组成，并且以流水线为基础进行数字运算处理。 MPL通过级联初始模块，基本模块，废弃模块和最后一级模块构成，并且仅对重要数据长度进行连续运算，而不会有任何过多的位。控制电路DCNT在运算循环的最后一级检测到运算结果的溢出时，向闭合门G1-G6发送0，从而仅在对应于参数的周期内将0插入到DR1-DR3中。在时分模式下连续输入MPL的系数F，通过寄存器ZR调整输入L（t）和定时，从而与输出同步信号SYN同步地从门G3发送输出W（t）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式