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1. 发明专利

JP2005268575A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2005268575A
公开(公告)日：2005-09-29
申请号：JP2004079791
申请日：2004-03-19
申请人： Elpida Memory Inc , Hitachi Ltd , Renesas Eastern Japan Semiconductor Inc , Renesas Technology Corp , エルピーダメモリ株式会社 , 株式会社ルネサステクノロジ , 株式会社ルネサス東日本セミコンダクタ , 株式会社日立製作所
发明人： TANIE HISAFUMI , KATAGIRI MITSUAKI , WATANABE YUJI , NAKAMURA ATSUSHI , SATO TOMOHIKO
IPC分类号： H05K1/02 , H01L21/56 , H01L21/60 , H01L23/12 , H01L23/31 , H01L23/48 , H01L25/065 , H01L25/10 , H01L25/18 , H05K1/11 , H05K3/34
CPC分类号： H05K1/111 , H01L21/563 , H01L23/3114 , H01L24/48 , H01L25/0657 , H01L25/105 , H01L2224/32225 , H01L2224/48091 , H01L2224/73203 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06565 , H01L2924/00014 , H01L2924/01087 , H01L2924/15311 , H01L2924/181 , H05K2201/09281 , H05K2201/094 , H05K2201/10734 , Y02P70/611 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To realize large capacity, high function, and space reduction by improving the reliability of a connection part between a semiconductor package and a mounting substrate to a thermal load in a semiconductor device.
SOLUTION: The semiconductor device 1 has the semiconductor package 2 and the mounting substrate 5 with a land 8 electrically connected to the semiconductor package 2 via a solder bump 4. A plurality of lines wherein a plurality of lands 8 are arranged are formed in the mounting substrate 5. At least one of the lands 8 constituting a line which is located in a nearest side to a main side constituting a semiconductor package outer edge has wiring 9 extending along the mounting substrate surface from the land 8. The wiring 9 is formed so that a connection part to the land 8 is positioned on a side close to a line which is orthogonal to the line at the center of the land 8 than a line connecting from the center of the land 8 to the center of the semiconductor package 2.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：通过将半导体封装和安装基板之间的连接部分的可靠性提高到半导体器件中的热负载来实现大容量，高功能和空间减小。解决方案：半导体器件1具有半导体封装2和安装基板5，其具有通过焊料凸块4电连接到半导体封装2的焊盘8.形成有多个焊盘8布置的多条线构成位于构成半导体封装外边缘的主要侧的最靠近的一行的焊盘8中的至少一个具有沿着安装基板表面从焊盘8延伸的布线9.布线9 形成为使得与焊盘8的连接部分位于靠近与焊盘8的中心处的线垂直的线的一侧，而不是从焊盘8的中心到半导体的中心连接的线包装2.版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JP2004071595A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2004071595A
公开(公告)日：2004-03-04
申请号：JP2002224459
申请日：2002-08-01
申请人： Elpida Memory Inc , Hitachi Ltd , Renesas Eastern Japan Semiconductor Inc , エルピーダメモリ株式会社 , 株式会社ルネサス東日本セミコンダクタ , 株式会社日立製作所
发明人： TOKIDA KENSUKE , TSUKUI SEIICHIRO , SAKAGUCHI YOSHIHIRO , SATO TOMOHIKO
IPC分类号： H01L23/36 , H01L25/10 , H01L25/11 , H01L25/18
CPC分类号： H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To improve the heat dissipation efficiency when a chip having a high heat release rate constitutes a tape carrier package (TCP) in a semiconductor device constituted of a single TCP and, at the same time, to reduce the thickness of the device to an extremely small value at which flexibility is not lost. SOLUTION: The module of the semiconductor device contains TCPs 10 and 20. The TCP 10 is provided with a memory chip 11 on one surface of a tape frame 12 and a heat dissipating sheet 14 on the other surface of the frame 12 and dissipates the heat released from the chip 11 from the whole surface of the sheet 14. The other TCP 20 is also constituted in the same way. The TCPs 10 and 20 respectively have signal line frames 13 and 23 the front ends of which are connected and fixed to a substrate 5 and which hold tape frames 12 and 22 while floating them in the atmosphere. A protective case 6 covers the TCPs 10 and 20 on the surface of the substrate 5. In this structure, the heat dissipation effect is improved by forming the substrate 5 and protective case 6 with materials having high coefficients of thermal conductivity, and connecting the heat dissipating sheets 14 and 24 to at least either one of the substrate 5 and case 6. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：为了提高散热效率，当具有高散热率的芯片构成由单个TCP构成的半导体器件中的载带封装（TCP）时，同时为了减少该装置的厚度达到极小的值，在此不会损失灵活性。解决方案：半导体器件的模块包含TCP 10和20. TCP 10在框架12的一个表面上设置有存储芯片11，在框架12的另一个表面上设置有散热片14，从芯片11的整个表面散发从芯片11释放的热量。另一个TCP 20也以相同的方式构成。 TCP10和20分别具有信号线框架13和23，其前端被连接并固定到基板5，并且在将它们浮在大气中的同时保持带框架12和22。保护壳6覆盖基板5表面上的TCP 10和20.在该结构中，通过用具有高导热系数的材料形成基板5和保护壳6，并且将热量将片材14和24分散到衬底5和壳体6中的至少任一个。版权所有（C）2004，JPO

3. 发明专利

JP2004165605A Semiconductor unit, semiconductor module, and memory system 有权
公开(公告)号：JP2004165605A
公开(公告)日：2004-06-10
申请号：JP2003103681
申请日：2003-04-08
申请人： Elpida Memory Inc , Hitachi Ltd , Renesas Eastern Japan Semiconductor Inc , エルピーダメモリ株式会社 , 株式会社ルネサス東日本セミコンダクタ , 株式会社日立製作所
发明人： SENBA SEIJI , ANPO HISASHI , ONO TAKAO , HOSOKAWA KOJI , NISHIO YOJI , NAKAMURA ATSUSHI , SATO TOMOHIKO
IPC分类号： G06F12/00 , G06F13/16 , G11C5/00 , G11C11/24 , H01L23/12 , H01L23/52 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L25/105 , H01L23/50 , H01L23/552 , H01L23/60 , H01L23/64 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2223/6627 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05599 , H01L2224/06136 , H01L2224/48091 , H01L2224/4824 , H01L2224/49171 , H01L2224/85399 , H01L2225/1023 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/014 , H01L2924/13091 , H01L2924/15173 , H01L2924/15192 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/19032 , H01L2924/19041 , H01L2924/19051 , H01L2924/19106 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/3025 , H05K1/112 , H05K1/14 , H05K1/181 , H05K2201/09236 , H05K2201/10159 , H05K2201/10545 , Y02P70/611 , H01L2224/45099 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor unit capable of a high-speed operation, by contracting the wiring length of a branch wiring existent in its signal wiring. SOLUTION: A semiconductor unit 104, constituting a memory device comprises a memory chip 120 and a package board 121, has three wiring layers. The wirings of power-supply surfaces 118 (a VDD surface), 119 (a GND surface) are formed in the package board 121, and the wiring of an intra-package DQ bus 114 is formed in an intermediate wiring layer, interposed between both the power-supply surfaces 118, 119. The memory device 120 has two DQ pins 112 inside the one intra-package DQ bus 114. The intra-package DQ bus 114 and a signal-terminal pad 115 of the memory chip 120 are connected through the intermediary of a via. The via, whereby the intra-package DQ bus 114 and the signal-terminal pad are connected, constitutes a branch wiring, as viewed from the two DQ pins. COPYRIGHT: (C)2004,JPO

4. 发明专利

JP2004079940A Memory-module heat radiating device 审中-公开
公开(公告)号：JP2004079940A
公开(公告)日：2004-03-11
申请号：JP2002241691
申请日：2002-08-22
申请人： Elpida Memory Inc , Hitachi Ltd , Renesas Eastern Japan Semiconductor Inc , エルピーダメモリ株式会社 , 株式会社ルネサス東日本セミコンダクタ , 株式会社日立製作所
发明人： ONO TAKAO , SATO TOMOHIKO , IWASAKI HIRONORI , TANAKA MITSUYA , SAKAGUCHI YOSHIHIRO
IPC分类号： H01L23/40
摘要： PROBLEM TO BE SOLVED: To provide a memory-module heat radiating device wherein it can cool memory modules efficiently at a low cost in a space saving way, and such works as its attachment and detachment are made easy, and further, it has such a high flexibility as to make it adaptable to the semiconductor memory modules having miscellaneous disposing pitches.
SOLUTION: The memory-module heat radiating device is the device interposed between semiconductor memory modules 7, 8 for performing the heat radiations of the semiconductor memory modules 7, 8, when disposing projectively in parallel with each other memory boards. A plurality of memory elements are so provided as to constitute respectively the semiconductor memory modules 7, 8. The memory-module heat radiating device has a thermal conduction component 1 having a thermal conductivity not lower than a predetermined value, and has an elastic component 2 exhibiting such a force that the thermal conduction component 1 abuts thereby against the adjacent semiconductor memory modules 7, 8 to each other.
COPYRIGHT: (C)2004,JPO

5. 发明专利

JP2005268241A Semiconductor package and system module 有权
标题翻译：半导体封装和系统模块
公开(公告)号：JP2005268241A
公开(公告)日：2005-09-29
申请号：JP2004073728
申请日：2004-03-16
申请人： Elpida Memory Inc , Renesas Eastern Japan Semiconductor Inc , Renesas Technology Corp , エルピーダメモリ株式会社 , 株式会社ルネサステクノロジ , 株式会社ルネサス東日本セミコンダクタ
发明人： ONO TAKAO , SATO TOMOHIKO , IWASAKI HIRONORI
IPC分类号： H01L23/12 , H01L23/02 , H01L23/13 , H01L23/498 , H01L25/10 , H01L25/11 , H01L25/18 , H05K1/02 , H05K3/34
CPC分类号： H01L23/49816 , H01L23/13 , H01L25/105 , H01L2225/1023 , H01L2225/1058 , H01L2924/0002 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H05K1/0271 , H05K3/3436 , H05K2201/09172 , H05K2201/10515 , Y02P70/613 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a surface mounting semiconductor package which has a high reliability and is low cost and has good electric characteristics such as low capacitance and low inductance by reducing solder distortion, and also to provide a system module.
SOLUTION: On the peripheral sides of a package substrate 1, slits 6 are formed on both sides of each solder ball 5 in a direction perpendicular to the pheripheral sides. Due to this structure, stress applied to the solder balls 5 can be relaxed and the distortion, deformation, and cracking of the solder balls 5 can be prevented.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种表面安装半导体封装，其具有高可靠性和低成本，并且通过减少焊料失真而具有诸如低电容和低电感的良好的电特性，并且还提供一种系统模块。解决方案：在封装基板1的周边上，在垂直于三边形的方向上在每个焊球5的两侧形成狭缝6。由于这种结构，可以减轻施加到焊球5的应力，并且可以防止焊球5的变形，变形和破裂。版权所有（C）2005，JPO＆NCIPI

6. 发明专利

JP2010146601A Semiconductor memory device and control method of same 审中-公开
标题翻译：半导体存储器件及其控制方法
公开(公告)号：JP2010146601A
公开(公告)日：2010-07-01
申请号：JP2008319643
申请日：2008-12-16
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： SATO TOMOHIKO
IPC分类号： G11C11/4099 , G11C11/4091
摘要： PROBLEM TO BE SOLVED: To secure a sufficient sense margin even though a reference potential is lowered according to the voltage drop of a driving voltage for a semiconductor memory device.
SOLUTION: The semiconductor memory device includes: a pair of bit lines consisting of bit lines 2a, 2b complementarily forming a pair each other; main word lines 3a, 3b arranged intersecting the bit lines 2a, 2b with respect to each of the bit lines 2a, 2b of a pair of bit lines; memory cells 4a, 4b arranged on the intersection of the bit lines 2a, 2b and the main word lines 3a, 3b and holding data as potentials; and a sense amplifier 1 connected to each of bit lines 2a, 2b of a pair of bit lines to amplify a potential difference between a pair of bit lines, which is caused by the change in potential of one side of the bit lines 2a, 2b according to reading of the data held by the memory cells 4a, 4b. The semiconductor memory device is provided with a potential raising means for raising each potential of the bit lines 2a, 2b of a pair of bit lines together before amplifying the potential difference by the sense amplifier 1 after the potential difference is caused between a pair of bit lines.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了确保足够的感测余量，即使根据半导体存储器件的驱动电压的电压降降低参考电位。解决方案：半导体存储器件包括：由位线2a，2b组成的一对位线，彼此互补地形成一对; 与位线2a，2b相对于一对位线的每个位线2a，2b布置的主字线3a，3b; 配置在位线2a，2b和主字线3a，3b的交点上的存储单元4a，4b，并将数据保持为电位; 以及连接到一对位线的位线2a，2b中的每一个的读出放大器1，以放大由位线2a，2b的一侧的电位变化引起的一对位线之间的电位差根据对存储单元4a，4b所保持的数据的读取。半导体存储器件设置有电位提升装置，用于在一对位之间引起电位差之后，将一对位线的位线2a，2b的每个电位升高到一起，然后在读出放大器1放大电位差之前，线。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2010287272A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2010287272A
公开(公告)日：2010-12-24
申请号：JP2009139320
申请日：2009-06-10
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： SATO TOMOHIKO
IPC分类号： G11C11/4091 , G11C11/4074
CPC分类号： G11C7/12 , G11C5/146
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which performs equalization at high speed without using a transistor high in breakdown strength for an equalized transistor of a bit line.
SOLUTION: The semiconductor device includes: first and second bit lines; a transistor in which one end is connected to the first bit line and another end is connected to the second bit line; and a substrate bias control circuit supplying first substrate bias voltage or second substrate bias voltage to the transistor. The equalization is performed at high speed by controlling the substrate bias potential of the transistor, and the increases of leak current when waiting and when activation are prevented.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种高速执行均衡的半导体器件，而不使用位线的均衡晶体管的击穿强度高的晶体管。解决方案：半导体器件包括：第一和第二位线; 晶体管，其一端连接到第一位线，另一端连接到第二位线; 以及向晶体管提供第一衬底偏置电压或第二衬底偏置电压的衬底偏置控制电路。通过控制晶体管的衬底偏置电位和等待时以及当激活被阻止时泄漏电流的增加，高速执行均衡。版权所有（C）2011，JPO＆INPIT

8. 发明专利

JP2004147458A Boosting circuit 审中-公开
标题翻译：升压电路
公开(公告)号：JP2004147458A
公开(公告)日：2004-05-20
申请号：JP2002311244
申请日：2002-10-25
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： SATO TOMOHIKO , MIYANO KAZUTAKA
IPC分类号： H02M3/07
CPC分类号： H02M3/073 , H02M2003/077
摘要： PROBLEM TO BE SOLVED: To provide a boosting circuit reduced in noise by suppressing an abrupt change in current at the start of operation.
SOLUTION: An oscillator circuit 20 outputs a plurality of oscillation signals ψ1 to ψn different in edge timings. An enable circuit 60 counts an edge from the start of boosting operation with respect to at least one of the oscillation signals ψ1 to ψn, and generates an enable signal that gives an instruction to a boosting capability control circuit 30 to keep boosting capabilities of pumping circuits 41 to 4n lowered until a count value reaches a set value. The boosting capability control circuit 30 controls the boosting capabilities of the pumping circuits 41 to 4n according to the enable signal. A pumping circuit 40 performs boosting operation by charging/discharging pumping capacities using the oscillation signals ψ1A to ψnA, and generates a boosting voltage VPP by combining output signals.
COPYRIGHT: (C)2004,JPO
摘要翻译：解决的问题：通过抑制开始运行时的电流突然变化来提供降低噪声的升压电路。解决方案：振荡器电路20输出边缘定时不同的多个振荡信号ψ1至ψn。使能电路60相对于振荡信号ψ1〜ψn中的至少一个对升压动作开始进行计数，并生成使能信号，其向升压能力控制电路30提供指令，以保持泵浦电路的升压能力 41〜4n降低，直到计数值达到设定值。升压能力控制电路30根据使能信号来控制泵浦电路41〜4n的升压能力。泵浦电路40通过使用振荡信号ψ1A〜ψnA对泵送容量进行充放电来进行升压动作，通过组合输出信号来生成升压电压VPP。版权所有（C）2004，JPO

9. 发明专利

JP2009026403A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2009026403A
公开(公告)日：2009-02-05
申请号：JP2007189767
申请日：2007-07-20
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： TANIMURA NAOYA , SATO TOMOHIKO , DONO CHIAKI
IPC分类号： G11C29/08 , G11C11/401 , G11C11/406
CPC分类号： G11C29/24 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/406 , G11C11/4076 , G11C29/50016 , G11C29/783
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which a test time of a refresh test of redundancy area is shortened.
SOLUTION: A cell array provided with a plurality of cells requiring refresh to hold data is provided with redundancy area provided with a plurality of redundant cells for replacing a defective cell of normal area in the cell array, a refresh counter circuit 19 generating a refresh address for the normal area performs re-arrangement of addresses in such a manner that an address of the redundancy area is arranged at a lower order side including LSB of the counter during a test of redundancy area.
COPYRIGHT: (C)2009,JPO&INPIT

10. 发明专利

JP2013004113A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2013004113A
公开(公告)日：2013-01-07
申请号：JP2011130908
申请日：2011-06-13
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： SATO TOMOHIKO
IPC分类号： G11C11/4091 , G11C11/401 , G11C11/4074
摘要： PROBLEM TO BE SOLVED: To avoid occurrence of an excessive boost pressure of a sense amplifier column without changing an overdrive time.SOLUTION: The semiconductor device includes: an overdrive wire 23-1 corresponding to a plurality of sense amplifier columns; a first capacitive element 61-1 having one end connected to the overdrive wire; a second capacitive element 61-2 having one end connected to the overdrive wire through a first switch 62-1; a second switch 27-1 for controlling supply and supply stop of a first voltage to the overdrive wire; and a control section for controlling activation of the plurality of the sense amplifiers, and simultaneously controlling the first switch and the second switch.
摘要翻译：要解决的问题：为了避免在不改变过驱动时间的情况下发生感测放大器列的过大的增压压力。解决方案：半导体器件包括：对应于多个读出放大器列的过驱动线23-1; 第一电容元件61-1，其一端连接到过驱动线; 第一电容元件61-2，其一端通过第一开关62-1连接到过驱动线; 第二开关27-1，用于控制对过驱动线的第一电压的供电停止; 以及控制部分，用于控制多个读出放大器的激活，同时控制第一开关和第二开关。版权所有（C）2013，JPO＆INPIT

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