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1. 发明专利

JP2012204618A Semiconductor chip and method of manufacturing the same, and semiconductor device 有权
标题翻译：半导体芯片及其制造方法和半导体器件
公开(公告)号：JP2012204618A
公开(公告)日：2012-10-22
申请号：JP2011067968
申请日：2011-03-25
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： IDE AKIRA , TORII YASUSHI
IPC分类号： H01L21/301 , H01L21/3205 , H01L21/768 , H01L23/522
CPC分类号： H01L23/562 , H01L21/308 , H01L21/76898 , H01L23/481 , H01L23/5384 , H01L23/585 , H01L25/0657 , H01L2224/16 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565
摘要： PROBLEM TO BE SOLVED: To prevent the rear-side chipping that may be generated in a dicing step from intruding into an active area where a through electrode exists.SOLUTION: A memory chip 1A is divided into regions of a scribe area SA, a guard ring area GA and an active area AA from a scribe center SC side. In an interlayer insulating film of the scribe area SA, first and second crack stops 3a and 3b for preventing surface-side chipping of the memory chip 1A are provided. A guard ring 4 is provided on the surface side of the guard ring area GA. On the other hand, on a semiconductor substrate 10 side of the guard ring area GA (the rear side of the memory chip 1A), a groove 5A for preventing rear-side chipping is provided. Due to this rear face chipping prevention groove 5A, intrusion of the chipping into a region where a supporting through electrode 2a and a through electrode for a signal and the like are formed can be prevented.
摘要翻译：要解决的问题：为了防止在切割步骤中可能产生的后侧切屑侵入到存在通孔的有源区域中。解决方案：存储芯片1A被划分成划线区域SA，保护环区域GA和来自划线中心SC侧的有源区域AA的区域。在划线区域SA的层间绝缘膜中，设置用于防止存储芯片1A的表面侧切片的第一和第二裂纹停止件3a和3b。保护环区域GA的表面侧设有保护环4。另一方面，在保护环区域GA（存储芯片1A的后侧）的半导体基板10侧，设置有用于防止背面破碎的槽5A。由于该后面切屑防止槽5A，能够防止在形成支撑用贯通电极2a和通过电极的区域形成切屑的侵入。版权所有（C）2013，JPO＆INPIT

2. 发明专利

JP2008153434A Equipment and method for manufacturing semiconductor device 有权
标题翻译：用于制造半导体器件的设备和方法
公开(公告)号：JP2008153434A
公开(公告)日：2008-07-03
申请号：JP2006339904
申请日：2006-12-18
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： TORII YASUSHI
IPC分类号： H01L21/304 , B24B37/04 , B24B37/30
CPC分类号： B24B37/32
摘要： PROBLEM TO BE SOLVED: To provide a retainer ring structure capable of stabilizing polishing uniformity in a wafer surface even when a retainer ring for CMP is worn. SOLUTION: Grooves 2a, 2b are prepared on the surface of the retainer ring 1, which contacts a polishing pad 8. The concentric grooves 2b are the grooves for changing the contact area of the retainer ring 1 with respect to the polishing pad 8 as the retainer ring 1 is worn by wafer polishing operations. The respective grooves 2b are formed to have the depth of 0.1 mm, 0.2 mm, 0.3 mm in order from the outer circumference to the inner circumference of the retainer ring 1. The grooves 2a formed to cross the retainer ring 1 are the grooves for promoting the introduction of a polishing agent to the surface of a semiconductor wafer 5 and facilitating the dechuck of a head 3 with respect to the semiconductor wafer 5. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：即使当用于CMP的保持环被磨损时，提供能够稳定晶片表面的抛光均匀性的保持环结构。
解决方案：在保持环1的与抛光垫8接触的表面上制备槽2a，2b。同心槽2b是用于改变保持环1相对于抛光垫的接触面积的槽如图8所示，通过晶片抛光操作佩戴保持环1。相应的槽2b形成为从保持环1的外周到内周的顺序为0.1mm，0.2mm，0.3mm的深度。形成为横过保持环1的槽2a是用于促进将抛光剂引入到半导体晶片5的表面，并且有助于相对于半导体晶片5去除头3的脱扣。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2013115382A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2013115382A
公开(公告)日：2013-06-10
申请号：JP2011262946
申请日：2011-11-30
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： TORII YASUSHI
IPC分类号： H01L23/522 , H01L21/3205 , H01L21/768
CPC分类号： H01L23/481 , H01L21/6835 , H01L21/7682 , H01L21/76898 , H01L23/3135 , H01L24/11 , H01L24/13 , H01L24/14 , H01L2221/68327 , H01L2221/6834 , H01L2221/68372 , H01L2224/0401 , H01L2224/05571 , H01L2224/11002 , H01L2224/1146 , H01L2224/13021 , H01L2224/13022 , H01L2224/13023 , H01L2224/13025 , H01L2224/13082 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/14156 , H01L2224/14181 , H01L2224/16146 , H01L2224/81193 , H01L2924/00012 , H01L2924/00014 , H01L2924/014 , H01L2224/05552
摘要： PROBLEM TO BE SOLVED: To provide a through electrode with an insulation ring whose workability and functionality are both enhanced.SOLUTION: Independent insulation rings 62a and 62b are formed by filling an insulation substance into insulation ring annular grooves CGa and CGb formed through dry etching. Also, TSV side wall insulation rings 61a and 61b are formed by covering side walls of TSV through holes THa and THb formed through dry etching with insulation films. Further, a TSV 7 is formed by filling a dielectric, such as copper, into remaining parts of the TSV through holes THa and THb with seed/barrier layers 71 in-between. Thicknesses of the TSV side wall insulation rings 61 are around a half of widths of the insulation ring annular grooves CG, in other words, thicknesses of the independent insulation rings 62. As a result, it is possible to set the thicknesses of the TSV side wall insulation rings 61 at around a third of the thicknesses of the TSV side wall insulation rings in the case where the TSV side wall insulation rings are provided independently.
摘要翻译：要解决的问题：为通孔提供绝缘环，其可加工性和功能性都得到增强。解决方案：通过将绝缘物质填充到通过干蚀刻形成的绝缘环环形沟槽CGa和CGb中，形成独立的绝缘环62a和62b。此外，TSV侧壁绝缘环61a和61b通过用绝缘膜覆盖通过干蚀刻形成的孔THa和THb覆盖TSV的侧壁而形成。此外，通过在其间插入种子/阻挡层71的孔THa和THb将诸如铜的电介质填充到TSV的剩余部分中形成TSV 7。 TSV侧壁绝缘环61的厚度是绝缘环形环CG的宽度的大约一半，换句话说，是独立绝缘环62的厚度。结果，可以设定TSV侧的厚度在TSV侧壁绝缘环独立设置的情况下，TSV侧壁绝缘环的三分之一厚度的壁绝缘环61。版权所有（C）2013，JPO＆INPIT

4. 发明专利

JP2007287787A Method and equipment for manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法和设备
公开(公告)号：JP2007287787A
公开(公告)日：2007-11-01
申请号：JP2006110850
申请日：2006-04-13
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： TORII YASUSHI
IPC分类号： H01L21/304 , B24B37/04 , B24B37/30
CPC分类号： B24B49/00 , B24B37/32
摘要： PROBLEM TO BE SOLVED: To suppress the deterioration of the in-plane uniformity of a polished wafer caused by the abrasion of a retainer ring in a polishing device of a semiconductor wafer. SOLUTION: The deterioration of the in-plane uniformity of a polished semiconductor wafer caused by a variation in the profile of the footprint of a retainer ring is compensated by measuring the amount of abrasion of the retainer ring at predetermined timing and changing the height or polishing conditions of the retainer ring more than reduction in the thickness of the retainer ring. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：为了抑制由半导体晶片的研磨装置中的保持环的磨损引起的抛光晶片的面内均匀性的劣化。解决方案：通过保持环的覆盖区的轮廓的变化引起的抛光的半导体晶片的面内均匀性的劣化通过在预定的时间测量保持环的磨损量来改变，并且改变保持环的高度或抛光条件大于保持环厚度的减小。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2013074263A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2013074263A
公开(公告)日：2013-04-22
申请号：JP2011214473
申请日：2011-09-29
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： TORII YASUSHI
IPC分类号： H01L21/60 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L21/6836 , H01L21/76898 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2221/6834 , H01L2224/0401 , H01L2224/05027 , H01L2224/05166 , H01L2224/05572 , H01L2224/05647 , H01L2224/06102 , H01L2224/11002 , H01L2224/11462 , H01L2224/1147 , H01L2224/13009 , H01L2224/13083 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/1403 , H01L2224/14181 , H01L2224/16146 , H01L2224/16225 , H01L2224/17055 , H01L2224/81193 , H01L2224/81203 , H01L2224/81815 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/15311 , H01L2924/15788 , H01L2924/351 , H01L2924/00012 , H01L2924/01047 , H01L2224/05552 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To solve such a problem that when stacking semiconductor chips each having a through electrode and interconnecting the through electrodes, a layer to be fluidized by heating, e.g., a solder layer, out of the metal bonding layers on the surface of a bump becoming the connection terminal of the through electrode may be collapsed and thinned thus lowering the bonding strength.SOLUTION: First and second sub-bumps 50, 68 are provided along with a normal bump structure (first and second main bumps 51, 69) on both principal surfaces of a semiconductor substrate. At least one of the first and second sub-bumps is made higher than the first and second main bumps, so that the sub-bumps are brought into contact with each other earlier than the main bumps when bonding a semiconductor chip. Consequently, the bonding margin of the main bumps is ensured, and thinning of a layer fluidized by heating, e.g., a solder layer 49, is minimized on the main bump.
摘要翻译：解决这样的问题：为了解决这样的问题，当堆叠具有通孔的半导体芯片和互连通孔时，通过加热例如焊料层而被流化的层从金属接合层变成直通电极的连接端子的凸块的表面可能被折叠和变薄，从而降低了接合强度。解决方案：第一和第二子凸块50,68与半导体衬底的两个主表面上的正常凸起结构（第一和第二主凸起51,69）一起提供。第一和第二子凸块中的至少一个被制成高于第一和第二主凸块，使得当接合半导体芯片时，子凸块比主凸起更早地彼此接触。因此，确保了主凸起的接合边缘，并且在主凸块上使诸如焊料层49的加热流化的层的薄化最小化。版权所有（C）2013，JPO＆INPIT

6. 发明专利

JP2013182985A Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2013182985A
公开(公告)日：2013-09-12
申请号：JP2012045236
申请日：2012-03-01
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： NAKAE MINORU , TORII YASUSHI
IPC分类号： H01L23/522 , H01L21/3205 , H01L21/768
摘要： PROBLEM TO BE SOLVED: To reduce metallic contamination from outside a semiconductor chip to an element region.SOLUTION: A semiconductor device comprises: insulation regions 4 which pierce a semiconductor substrate in a thickness direction; and a defect layer 3 introduced to the semiconductor substrate around the insulation regions. The insulation regions 4 are arranged on an outer peripheral region of a semiconductor chip, for example, at distances to at least link the defect layer 3. The defect layer 3 exhibits a gettering effect of trapping a metal impurity.
摘要翻译：要解决的问题：为了减少从半导体芯片外部到元件区域的金属污染。解决方案：半导体器件包括：在厚度方向上刺穿半导体衬底的绝缘区域4; 以及在绝缘区域周围引入到半导体衬底的缺陷层3。绝缘区域4布置在半导体芯片的外周区域上，例如至少连接缺陷层3的距离。缺陷层3表现出捕获金属杂质的吸气效应。

7. 发明专利

JP2007324458A Method for manufacturing semiconductor device, and manufacturing equipment of the semiconductor device 有权
标题翻译：制造半导体器件的方法和半导体器件的制造设备
公开(公告)号：JP2007324458A
公开(公告)日：2007-12-13
申请号：JP2006154741
申请日：2006-06-02
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： TORII YASUSHI
IPC分类号： H01L21/304 , B24B37/00 , B24B37/005 , H01L21/3205 , H01L21/321 , H01L21/768
CPC分类号： B24B37/042 , B24B49/16
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device and a manufacturing equipment of the semiconductor device, that can uniformly polish the surface of a semiconductor wafer. SOLUTION: In the method for manufacturing the semiconductor device, the semiconductor wafer is pressed against a polishing pad, to polish the semiconductor wafer and the method comprises an optimum condition calculating step of acquiring polishing condition, based on the hardness of the polishing pad, and a step of polishing the semiconductor wafer subject to the acquired polishing condition. COPYRIGHT: (C)2008,JPO&INPIT

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