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1. 发明专利

JP2008060529A Power electronic package having two sheets of substrate mounting a plurality of electronic components 审中-公开
标题翻译：具有两片基板的电力电子封装安装了大量的电子元件
公开(公告)号：JP2008060529A
公开(公告)日：2008-03-13
申请号：JP2007114784
申请日：2007-04-24
申请人： Denso Corp , Univ Of Cambridge , Univ Of Sheffield , ケンブリッジ大学 , シェフィールド大学 , 株式会社デンソー
发明人： MALHAN RAJESH KUMAR , JOHNSON MARK , RASHID JEREMY
IPC分类号： H01L23/48 , H01L25/07 , H01L25/18
CPC分类号： H01L24/72 , H01L24/01 , H01L24/33 , H01L25/072 , H01L25/18 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/15747 , H01L2924/15787 , H01L2924/30107 , H01L2924/351 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To enhance heat dissipation performance of a power electronic package having two sheets of substrate mounting a plurality of electronic components, and to reduce stress applied to the electronic components. SOLUTION: The power electronic package comprises first and second high thermal conductivity insulating nonplanar substrates, and a plurality of electronic components mounted, respectively, on the first and second high thermal conductivity insulating nonplanar substrates. The first and second high thermal conductivity insulating nonplanar substrates are mutually bonded in a plurality of bond regions and mechanical separation between the first and second high thermal conductivity insulating nonplanar substrates is controlled by the number, arrangement, and material of the bond regions. Mechanical separation imparts a compression force toward the net axial direction in the electronic component. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了增强具有安装多个电子部件的两片基板的电力电子封装的散热性能，并且减小施加到电子部件的应力。解决方案：功率电子封装包括第一和第二高导热绝缘非平面基板和分别安装在第一和第二高导热绝缘非平面基板上的多个电子部件。第一和第二高导热绝缘非平面基板在多个接合区域中相互接合，并且第一和第二高导热绝缘非平面基板之间的机械分离由接合区域的数量，布置和材料控制。机械分离在电子部件中向网轴方向施加压缩力。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2008060531A Power electronic package having two sheets of substrate mounting a plurality of semiconductor chips and electronic components 有权
标题翻译：具有两片基板的功率电子封装安装多个半导体晶体管和电子元件
公开(公告)号：JP2008060531A
公开(公告)日：2008-03-13
申请号：JP2007126042
申请日：2007-05-10
申请人： Denso Corp , Univ Of Cambridge , Univ Of Sheffield , ケンブリッジ大学 , シェフィールド大学 , 株式会社デンソー
发明人： MALHAN RAJESH KUMAR , JOHNSON MARK , BUTTAY CYRIL , RASHID JEREMY , UDREA FLORIN
IPC分类号： H01L25/07 , H01L25/18
CPC分类号： H01L23/49844 , H01L23/5385 , H01L24/31 , H01L24/83 , H01L25/072 , H01L25/18 , H01L2224/33 , H01L2224/81894 , H01L2224/83801 , H01L2224/83894 , H01L2924/01079 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/13062 , H01L2924/13091 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To enhance heat dissipation performance of a power electronic package having two sheets of substrate mounting a plurality of semiconductor chips and electronic components. SOLUTION: A plurality of semiconductor chips and electronic components are arranged between first and second high thermal conductivity insulating nonplanar substrates. Electric conductor layers of the first and second high thermal conductivity insulating nonplanar substrates are connected mechanically and electrically with the semiconductor chips and electronic components. The first and second high thermal conductivity insulating nonplanar substrates further include a plurality of raised regions, i.e. posts, being bonded mutually. The number and arrangement of the raised regions, i.e. posts, and the profile of each region, i.e. post, are adjusted to bring about mechanical separation between the first and second high thermal conductivity insulating nonplanar substrates. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提高具有安装多个半导体芯片和电子部件的两片基板的电力电子封装的散热性能。解决方案：多个半导体芯片和电子部件布置在第一和第二高导热绝缘非平面基板之间。第一和第二高导热绝缘非平面基板的导体层与半导体芯片和电子部件机械地和电气地连接。第一和第二高导热绝缘非平面基板还包括多个相互接合的凸起区域，即柱。调整凸起区域（即柱子）的数量和布置以及每个区域（即柱子）的轮廓，以在第一和第二高导热性绝缘非平面基板之间产生机械分离。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2006093382A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2006093382A
公开(公告)日：2006-04-06
申请号：JP2004276565
申请日：2004-09-24
申请人： Denso Corp , Hitachi Ltd , 株式会社デンソー , 株式会社日立製作所
发明人： OYANAGI TAKASUMI , WATANABE TOKUO , SAKAKIBARA TOSHIO , YAMAMOTO TAKESHI , NAKAMURA HIROKI , MALHAN RAJESH KUMAR
IPC分类号： H01L27/095 , H01L21/822 , H01L21/8232 , H01L27/04 , H01L27/06 , H01L29/47 , H01L29/80 , H01L29/861 , H01L29/872
CPC分类号： H01L29/1066 , H01L29/7722 , H01L29/8083
摘要： PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device which incorporates a temperature measuring diode that can be operated at a high temperature and which can be used under a high temperature environment.
SOLUTION: When a structure where grooves 110 and 111 are used for control regions 12 and 14 is adopted as an electrostatic induction transistor, a normally-off device can be obtained in accordance with a distance between control layers. Normally-off device is used as inter-element separation, and a hetero-junction diode 114 (or pn junction diode) is constituted of silicon carbide and polycrystalline silicon. Inter-element separation is realized by grounding a deep p-type third layer 30. The temperature measuring diode can be formed between an n-type fourth layer on an inner side and the other face of a substrate.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种碳化硅半导体器件，其包含可在高温下操作并可在高温环境下使用的温度测量二极管。解决方案：当将控制区域12和14用作沟槽110和111的结构用作静电感应晶体管时，可以根据控制层之间的距离获得常关器件。正常关断器件用作元件间隔离，异质结二极管114（或pn结二极管）由碳化硅和多晶硅构成。通过使深p型第三层30接地来实现元件间分离。温度测量二极管可以形成在内侧的n型第四层和衬底的另一面之间。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2012151484A Silicon carbide semiconductor device and method of manufacturing same 有权
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：JP2012151484A
公开(公告)日：2012-08-09
申请号：JP2012053176
申请日：2012-03-09
申请人： Denso Corp , 株式会社デンソー
发明人： TAKEUCHI YUICHI , MALHAN RAJESH KUMAR , SUGIYAMA NAOHIRO
IPC分类号： H01L29/812 , H01L21/336 , H01L21/337 , H01L21/338 , H01L29/12 , H01L29/78 , H01L29/808
摘要： PROBLEM TO BE SOLVED: To suppress excessive drain currents that occur when a gate voltage approaches a threshold value.SOLUTION: A JFET structure is discouraged from being configured at the tip part of a trench 6 because an ntype channel layer 7 formed at the tip part of the trench 6 becomes thicker in film thickness than a portion positioned at the major side of the trench 6. As an example, the tip part of the trench 6 is completely filled with a ptype region 20. Consequently, the effect which is caused by the fact that a threshold value of the JFET structure at the tip part of the trench 6 is deviated from the threshold value of the JFET structure at the portion positioned at the major side of the trench 6, is prevented. Thus, such SiC semiconductor device as has a structure to suppress an excessive drain current that occurs when a gate voltage approaches the threshold value can be provided.
摘要翻译：要解决的问题：抑制当栅极电压接近阈值时发生的过多的漏极电流。解决方案：阻止JFET结构配置在沟槽6的尖端部分，因为形成在沟槽6的尖端部分的n - / SP>型沟道层7 厚度比沟槽6的长边部分的膜厚变厚。作为一个例子，沟槽6的顶端部分被完全填充为“ 因此，由于沟槽6的尖端部分的JFET结构的阈值与位于沟槽6的主侧的部分处的JFET结构的阈值偏离的事实引起的效果，被阻止因此，可以提供具有抑制当栅极电压接近阈值时发生的过度的漏极电流的结构的这种SiC半导体器件。版权所有（C）2012，JPO＆INPIT

5. 发明专利

JP2011159714A Silicon carbide semiconductor device and manufacturing method therefor 审中-公开
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：JP2011159714A
公开(公告)日：2011-08-18
申请号：JP2010018747
申请日：2010-01-29
申请人： Denso Corp , 株式会社デンソー
发明人： MALHAN RAJESH KUMAR , KUZUHARA MASAAKI
IPC分类号： H01L21/337 , H01L21/28 , H01L21/338 , H01L29/417 , H01L29/423 , H01L29/47 , H01L29/49 , H01L29/808 , H01L29/812 , H01L29/872
CPC分类号： H01L29/12 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To reduce a capacitance between a gate and a source and between the gate and a drain, and to suppress a rise in a gate applied voltage needed for turning on a JFET.
SOLUTION: A p
+ -type gate region 6 is formed on via i-type (intrinsic semiconductor) side wall layer 5 formed in a recession 4c. This configuration eliminates the need of forming a p
- -type layer having a dopant concentration lower than that of a p
+ -type gate region 6 between the n
+ -type layer 4 and the p
+ -type gate region 6. As a result, the width of a depletion layer spreading inside an n
- -type channel layer 3 is controlled by the high concentration p
+ -type gate region 6 in direct contact with the n
- -type channel layer 3. Hence a rise in a gate applied voltage is suppressed as compared to a case where the p
- -type layer is formed between the n
+ -type layer 4 and the p
+ -type gate region 6. The side faces of the p
+ -type gate region 6 are separated from the n
+ -type layer 4 via the i-type side wall layer 5. This reduces a capacitance between a gate and a source and between the gate and a drain.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了减小栅极和源极之间以及栅极和漏极之间的电容，并抑制导通JFET所需的栅极施加电压的上升。解决方案：在凹陷部4c形成的通孔i型（本征半导体）侧壁层5上形成p + 型栅极区域6。这种配置消除了在n + 型层之间形成掺杂剂浓度低于ap + 型栅极区域6的p < SP>型层4和p + 型栅极区6.结果，在n - / SP>型沟道层3内扩展的耗尽层的宽度由与p 型沟道层3直接接触的高浓度p + 型栅极区域6控制。因此，栅极施加电压的上升被抑制与在p + 型层4和p + 型层4之间形成p - SP>型层的情况相比，区域6.通过i型侧壁层5将p + 型栅极区域6的侧面与n + 型层4分离。减小栅极和源极之间以及栅极和漏极之间的电容。版权所有（C）2011，JPO＆INPIT

6. 发明专利

JP2011165763A Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2011165763A
公开(公告)日：2011-08-25
申请号：JP2010024477
申请日：2010-02-05
申请人： Denso Corp , 株式会社デンソー
发明人： MALHAN RAJESH KUMAR , TAKEUCHI YUICHI
IPC分类号： H01L21/337 , H01L29/41 , H01L29/417 , H01L29/808
摘要： PROBLEM TO BE SOLVED: To reduce capacitance between a gate and a source, and between a gate and a drain, and prevent a gate for applying a voltage required for turning on a JFET (junction field effect transistor) from becoming high.
SOLUTION: A p
+ type gate region 4 is directly formed on the surface of an n
- type channel layer 2 so that a part away from the n
- type channel layer 2 becomes wide compared to a part contacting the n
- type channel layer 2 out of the p
+ type gate region 4. The wide part of the p
+ type gate region 4 is made to be separated from the n
- type channel layer 2 by a predetermined distance. For example, a recess 2a is formed on the n
- type channel layer 2, and the p
+ type gate region 4 is formed in the recess 2a.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了减小栅极和源极之间以及栅极和漏极之间的电容，并且防止用于施加导通JFET（结型场效应晶体管）所需的电压的栅极变高。解决方案：在n - / SP>型沟道层2的表面上直接形成p + 型栅极区域4，使得远离n + 型栅极区域4中的n - 型沟道层2的部分相比，> - 型沟道层2变宽。将p + 型栅极区域4的一部分从n - / SP>型沟道层2分离预定距离。例如，凹槽2a形成在n型SP型沟道层2上，并且p + SP型栅极区4形成在凹槽2a中。版权所有（C）2011，JPO＆INPIT

7. 发明专利

JP2011134971A Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2011134971A
公开(公告)日：2011-07-07
申请号：JP2009294801
申请日：2009-12-25
申请人： Denso Corp , 株式会社デンソー
发明人： MALHAN RAJESH KUMAR , SUGIYAMA NAOHIRO
IPC分类号： H01L21/337 , H01L21/28 , H01L27/095 , H01L29/417 , H01L29/423 , H01L29/808
CPC分类号： H01L29/808 , H01L29/1058 , H01L29/1066 , H01L29/1608 , H01L29/66068
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device where a D-mode element and an E-mode element are combined, and also to provide a method of manufacturing the semiconductor device. SOLUTION: By providing a recess 2a and a projection 2b at places for setting channel regions in a D-mode JFET and an E-mode JFET respectively, an n-type channel layer 3 having a different thickness is formed on the same substrate. Since JFETs operating in D and E modes are provided on the same substrate by the n-type channel layer 3 having a different thickness, an SiC semiconductor where the D-mode and E-mode JFETs are combined is achieved even by SiC. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供组合D模元件和E模元件的半导体器件，并且还提供制造半导体器件的方法。解决方案：通过在D型JFET和E型JFET中设置沟道区的位置设置凹部2a和突起2b，在其上形成具有不同厚度的n型沟道层3 基质。由于通过具有不同厚度的n型沟道层3在D和E模式中工作的JFET被提供在相同的衬底上，所以即使通过SiC也可实现组合D模式和E模JFET的SiC半导体。版权所有（C）2011，JPO＆INPIT

8. 发明专利

JP2011134969A Silicon carbide semiconductor device and method of manufacturing the same 审中-公开
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：JP2011134969A
公开(公告)日：2011-07-07
申请号：JP2009294798
申请日：2009-12-25
申请人： Denso Corp , 株式会社デンソー
发明人： TAKEUCHI YUICHI , MALHAN RAJESH KUMAR
IPC分类号： H01L21/337 , H01L21/265 , H01L27/095 , H01L29/78 , H01L29/808
摘要： PROBLEM TO BE SOLVED: To form an element even without requiring epitaxial growth, and to prevent bunching from occurring.
SOLUTION: No epitaxial growth is required and each region for composing an element is formed only by ion implantation, and an on substrate without including an off angle is used as an SiC substrate 1, thus preventing bunching from occurring due to heat treatment for activating an ion implantation region, thereby providing an SiC semiconductor device by growing an element even if no epitaxial growth is required and preventing bunching from occurring.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：即使不需要外延生长也能形成元件，并且防止发生聚束。解决方案：不需要外延生长，并且仅通过离子注入形成用于组成元件的每个区域，并且使用不包括偏角的基板作为SiC基板1，从而防止由于热处理而发生聚束用于激活离子注入区域，从而通过生长元件即使不需要外延生长并防止发生聚束来提供SiC半导体器件。版权所有（C）2011，JPO＆INPIT

9. 发明专利

JP2006041163A Method for manufacturing silicon carbide semiconductor device 有权
标题翻译：制造碳化硅半导体器件的方法
公开(公告)号：JP2006041163A
公开(公告)日：2006-02-09
申请号：JP2004218542
申请日：2004-07-27
申请人： Denso Corp , 株式会社デンソー
发明人： TAKEUCHI YUICHI , MALHAN RAJESH KUMAR
IPC分类号： H01L21/205 , H01L29/161
摘要： PROBLEM TO BE SOLVED: To prevent any 3C-SiC defect from mixing in an impurity region, and to surely remove a selection mask.
SOLUTION: The growth upper face of an impurity region 7 to be formed in a trench 5 is set below the lower face of a carbon film 2 as a selection mask. That is, the growth upper face of the impurity region 7 to be formed in the trench 5 is suppressed to the lower face of the carbon film 2. Thus, it is possible to suppress the horizontal enlargement of the impurity region 7, and to prevent the polymorphism mixing of a 3C-SiC film 8 to be generated when the impurity region is horizontally grown.
COPYRIGHT: (C)2006,JPO&NCIPI

10. 发明专利

JP2012079795A Semiconductor device having junction field-effect transistor and method of manufacturing the same 有权
标题翻译：具有连接场效应晶体管的半导体器件及其制造方法
公开(公告)号：JP2012079795A
公开(公告)日：2012-04-19
申请号：JP2010221449
申请日：2010-09-30
申请人： Denso Corp , 株式会社デンソー
发明人： MALHAN RAJESH KUMAR
IPC分类号： H01L21/337 , H01L21/76 , H01L29/06 , H01L29/47 , H01L29/80 , H01L29/808 , H01L29/872
CPC分类号： H01L29/8083 , H01L29/0661 , H01L29/1608 , H01L29/42316 , H01L29/66068 , H01L29/872
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having a junction field effect transistor (JFET) with a structure capable of further minimizing a contact structure between a buried gate layer and gate wiring.SOLUTION: A p-type contact buried layer 14 formed in a trench 13 electrically connects a buried gate layer 10 and gate wiring 12. For this reason, the width of the trench 13 in which only the p-type contact buried layer 14 is disposed can be narrow compared to a trench in which, for example, an interlayer insulating film and gate wiring are disposed, like a conventional semiconductor device. Consequently, this can form the semiconductor device having a JFET with a structure capable of further minimizing the contact structure between the buried gate layer 10 and the gate wiring 12.
摘要翻译：要解决的问题：提供一种具有结型场效应晶体管（JFET）的半导体器件，其具有能够进一步最小化掩埋栅极层与栅极布线之间的接触结构的结构。解决方案：形成在沟槽13中的p + 型接触掩埋层14电连接掩埋栅极层10和栅极布线12.为此，其中仅设置p + / SP>型接触掩埋层14的沟槽13可以比其中例如层间绝缘膜和栅极布线为像传统的半导体器件那样放置。因此，这可以形成具有能够进一步最小化掩埋栅极层10和栅极布线12之间的接触结构的结构的JFET的半导体器件。版权所有：（C）2012，JPO＆INPIT

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