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1. 发明专利

JP2006073622A Semiconductor apparatus, package substrate therefor and manufacturing method thereof 有权
标题翻译：半导体器件，其封装基板及其制造方法
公开(公告)号：JP2006073622A
公开(公告)日：2006-03-16
申请号：JP2004252568
申请日：2004-08-31
申请人： Denso Corp , Nec Electronics Corp , Necエレクトロニクス株式会社 , 株式会社デンソー
发明人： HAYASHI EISHU , SUZUKI KATSUNOBU , OIKAWA RYUICHI , NAKAKOSHI MAKOTO , SERA NAOKO , MURAI TADASHI , OGIWARA CHIHO , KATAOKA RYOHEI , KONDO KOJI , YOKOCHI TOMOHIRO
IPC分类号： H01L23/12
CPC分类号： H05K3/4632 , H01L23/49816 , H01L23/49827 , H01L2224/16 , H01L2224/16225 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H05K1/0271 , H05K1/114 , H05K3/4617 , H05K2201/0129 , H05K2201/0394 , H05K2201/068 , H05K2201/09063 , H05K2201/096 , H05K2201/09781 , H05K2201/2009 , H05K2203/1178 , H01L2924/00 , H01L2224/0401
摘要： PROBLEM TO BE SOLVED: To provide a package substrate for a semiconductor apparatus which is easily manufactured, easily multilayered, and high reliable in electric connection. SOLUTION: A film-like insulating body 10 comprises a conductive pattern 4 formed on its surface, and a conductive via 9 that penetrates in thickness direction. A plurality of the insulting body 10 are stacked together, collectively pressurized, and heated for integration. At one outermost layer of a multilayer substrate 1, a plurality of connection terminals 6 are exposed outside to which the connection bump 5 of an LSI chip 2 is fixed. At the outermost layer on the opposite side, many metal pads 7 are provided with a solder ball 8 fixed to each metal pad 7, to constitute a ball grid array (BGA) structure for connection to a motherboard 3. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供一种容易制造，容易多层化并且电连接高可靠性的半导体装置用封装基板。解决方案：膜状绝缘体10包括在其表面上形成的导电图案4和在厚度方向上穿透的导电通孔9。将多个绝缘体10堆叠在一起，共同加压并加热以进行一体化。在多层基板1的一个最外层，多个连接端子6暴露在LSI芯片2的连接凸块5固定的外部。在相对侧的最外层，许多金属焊盘7设置有固定到每个金属焊盘7的焊球8，以构成用于连接到母板3的球栅阵列（BGA）结构。版权所有（ C）2006，JPO＆NCIPI

2. 发明专利

JP2009276874A Method for designing semiconductor package substrate 有权
标题翻译：用于设计半导体封装衬底的方法
公开(公告)号：JP2009276874A
公开(公告)日：2009-11-26
申请号：JP2008125517
申请日：2008-05-13
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： OIKAWA RYUICHI
IPC分类号： G06F17/50 , H01L23/12
CPC分类号： G06F17/5068 , G06F2217/40 , H01L23/66 , H01L27/0207 , H01L28/40 , H01L2223/6627 , H01L2223/6655 , H01L2924/0002 , H01L2924/1903 , H01L2924/19051 , H01L2924/3011 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To design a semiconductor package substrate for achieving impedance matching in primary mounting of a semiconductor chip and in secondary mounting to a secondary mounting substrate without deteriorating signal characteristics.
SOLUTION: When the impedance is deviated from a reference value, a circuit is designed for generating a reflected wave to cancel the reflected wave thus generated. Individual structural parts in a transmission line are intentionally designed to be deviated from a standard impedance reversely under a fine control. By this method, the impedance matching between the input and output impedance of the semiconductor element and the transmission line is achieved. As a result, the terminal impedance of the component of the semiconductor circuit and the semiconductor package substrate is adjusted to 50 Ohm, so that a good signal characteristic can be obtained.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：设计用于在半导体芯片的初级安装中实现阻抗匹配并在二次安装到二次安装基板的半导体封装基板，而不会降低信号特性。解决方案：当阻抗偏离参考值时，电路被设计为产生反射波以抵消由此产生的反射波。传输线中的单个结构部件有意设计为在精细控制下相反地偏离标准阻抗。通过这种方法，实现了半导体元件和传输线的输入和输出阻抗之间的阻抗匹配。结果，将半导体电路和半导体封装基板的部件的端子阻抗调节为50欧姆，从而可以获得良好的信号特性。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2006258667A Rf impedance measuring device of package substrate 审中-公开
标题翻译： RF阻抗测量装置的封装基板
公开(公告)号：JP2006258667A
公开(公告)日：2006-09-28
申请号：JP2005077946
申请日：2005-03-17
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： OIKAWA RYUICHI
IPC分类号： G01R27/02 , G01R1/073 , G01R27/28 , G01R31/28
CPC分类号： G01R31/2896
摘要： PROBLEM TO BE SOLVED: To provide an RF impedance measuring device capable of accurately measuring RF impedance (S parameter) especially of a power source/GND system line of a package substrate to a high frequency region. SOLUTION: An RF probe 210 is directly brought into contact with terminals 201 formed on the front and back surfaces of the package substrate 200, thereby measuring the RF impedance (S parameter) between the terminals. The RF probe 210 is directly brought into contact with a substrate 240 for phase calibration arranged horizontally and perpendicularly to the installed package substrate 200 by a rotating mechanism 220 connected to the RF probe 210. The phase difference between the terminals of the package substrate 200 is measured, and the measured value of the RF impedance (S parameter) is calibrated with this phase difference. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种RF阻抗测量装置，其能够将封装衬底的特别是电源/ GND系统线的RF阻抗（S参数）精确地测量到高频区域。解决方案：RF探针210直接与形成在封装衬底200的前表面和后表面上的端子201接触，从而测量端子之间的RF阻抗（S参数）。 RF探针210直接与用于通过连接到RF探针210的旋转机构220水平并垂直于安装的封装衬底200布置的用于相位校准的衬底240接触。封装衬底200的端子之间的相位差为测量，并用该相位差校准RF阻抗（S参数）的测量值。版权所有（C）2006，JPO＆NCIPI

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