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1. 发明专利

JP2010025688A Method for manufacturing microchip 有权
标题翻译：制造MICROCHIP的方法
公开(公告)号：JP2010025688A
公开(公告)日：2010-02-04
申请号：JP2008185972
申请日：2008-07-17
申请人： Dainippon Printing Co Ltd , 大日本印刷株式会社
发明人： OZAWA YU , DAITO RYOICHI , FUJIMOTO KOJI , YAMAGUCHI MASATAKA
IPC分类号： G01N35/08 , C03C27/10 , G01N37/00
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing microchips having an electrode, allowing observation by transmitted light, and suppressing machining failure. SOLUTION: In the method for manufacturing the microchip 10 including a glass base material 11 for a through-hole, a main glass base material 12, and a channel 21, first of all, the main glass base material 12 and a silicon-including base material 20 are prepared, and the electrode 24 is provided on the silicon-including base material 20, and a recessed part 25 is formed on the main glass base material 12. Then, the silicon-including base material 20 is bonded onto the main glass base material 12, and the electrode 24 provided on the silicon-including base material 20 is stored in the recessed part 25 on the main glass base material 12. Then, polishing is performed onto the silicon-including base material 20 on the main glass base material 12 to form a prescribed thickness of the silicon-including base material 20, and the channel 21 is formed on the silicon-including base material 20 by etching. Thereafter, the glass base material 11 for the through-hole is bonded onto the silicon-including base material 20. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造具有电极的微芯片的方法，允许通过透射光观察并抑制加工失败。解决方案：在包括用于通孔的玻璃基材11，主玻璃基材12和通道21的微芯片10的制造方法中，首先，将主玻璃基材12和硅 - 包括基材20，并且将电极24设置在含硅基材20上，并且在主玻璃基材12上形成凹部25.然后，将含硅基材20接合到将主玻璃基材12和设置在含硅基材20上的电极24储存在主玻璃基材12的凹部25中。然后，在含硅基材20上进行研磨主玻璃基材12，以形成含硅基材20的规定厚度，通过蚀刻在含硅基材20上形成通道21。此后，将用于通孔的玻璃基材11接合到含硅基材20上。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2007067335A Through-hole substrate filled with conductive material 审中-公开
标题翻译：通孔填充导电材料
公开(公告)号：JP2007067335A
公开(公告)日：2007-03-15
申请号：JP2005254919
申请日：2005-09-02
申请人： Dainippon Printing Co Ltd , 大日本印刷株式会社
发明人： YAMAGUCHI MASATAKA , TAKANO TAKAMASA , NAKAJO SHIGEKI
IPC分类号： H05K1/05 , H05K1/11 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a through-hole substrate which indicates superior transmission characteristics, even in a high frequency region. SOLUTION: A core plate 1 made of silicon is provided, a conductive material 3 is filled inside a through-hole 2 formed on the core plate, and makes the front and back of the core plate electrically continuous. By turning the specific resistance of the silicon that forms the core plate to be 100 Ω cm or larger, the through-hole substrate filled with the conductive material is obtained which indicates superior transmission characteristics, even in a high-frequency region of 20 GHz, for instance, loss is reduced in the high-frequency region, and electronic apparatuses are miniaturized and further made light in weight. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：即使在高频区域中也提供了表现出优异传输特性的通孔基板。解决方案：提供由硅制成的芯板1，将导电材料3填充在形成在芯板上的通孔2的内部，并使芯板的前后电连续。通过将形成芯板的硅的比电阻转换为100Ωcm以上，即使在20GHz的高频区域中，也可以获得充满导电性材料的通孔基板，其表现出良好的传输特性，例如，高频区域的损耗降低，电子设备小型化，重量轻。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2006005053A Electronic component built-in wafer 有权
标题翻译：电子元件内置波形
公开(公告)号：JP2006005053A
公开(公告)日：2006-01-05
申请号：JP2004178089
申请日：2004-06-16
申请人： Dainippon Printing Co Ltd , 大日本印刷株式会社
发明人： YAMAGUCHI MASATAKA , KURAMOCHI SATORU , TAKANO ATSUSHI
IPC分类号： H01L25/18 , H01G4/33 , H01L23/12 , H01L25/065 , H01L25/07
CPC分类号： H01L24/97 , H01L24/82 , H01L2224/24 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/09701 , H01L2224/82 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide an electronic component built-in wafer which can manufacture an electronic component built-in module usable in a plurality of stacks. SOLUTION: The electronic component built-in wafer comprises a wafer board 21 which is zoned for forming a plurality of faces by the dicing area 12 of a predetermined width, an electronic component built-in recess 22 every face formation, an electronic component 31 contained in each recess, and a plurality of wires 25 arranged on a wafer board through an insulating layer 24 so as to be connected with a terminal 32 of the electronic component every face formation. These wires have a bump pad 26 or a wire bonding pad, and a both-side conducting pad 27 at a pointed end thereof. The both-side conducting pad 27 is located in the dicing area and has a fine opening 27a at a substantial center, and the wafer board is exposed to this fine opening 27a. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够制造可用于多个堆叠的电子部件内置模块的电子部件内置晶片。电子部件内置晶片包括晶片板21，其被划分为通过预定宽度的切割区域12形成多个面，电子部件内置凹槽22，每个面形成，电子部件每个凹部中包含的部件31和通过绝缘层24布置在晶片板上的多条导线25，以便每个面形成与电子部件的端子32连接。这些线具有凸块焊盘26或引线接合焊盘，以及位于其尖端的双面导电焊盘27。双面导电焊盘27位于切割区域中并且在大致中心处具有微细开口27a，并且晶片板暴露于该微小开口27a。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2006005052A Multilayered wiring board and its manufacturing method 有权
标题翻译：多层接线板及其制造方法
公开(公告)号：JP2006005052A
公开(公告)日：2006-01-05
申请号：JP2004178088
申请日：2004-06-16
申请人： Dainippon Printing Co Ltd , 大日本印刷株式会社
发明人： KURAMOCHI SATORU , YAMAGUCHI MASATAKA
IPC分类号： H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a multilayered wiring board and its manufacturing method, wherein a high density wiring is possible, and the characteristic impedance matching of a signal transmission in a conduction between both the sides of a core board is possible, and a semiconductor chip can be mounted stably and reliably.
SOLUTION: In the multilayered wiring board which comprises a wiring formed via an electric insulating layer on the core board, the core board comprises a plurality of through holes and a both-side conduction composed of a conductive material located in these through holes. The both-side conduction has a coaxial structure which comprises a center line and a coaxial peripheral line located so as to surround this center line, and also the coaxial peripheral line has a notch, at least at one location in the circumferential direction. Further, each wiring is all arranged on the core board for connecting the center line with the coaxial peripheral line, and the wiring for connecting with the center line is passed through a region where the notch is exist.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供一种可以进行高密度布线的多层布线板及其制造方法，并且可以在芯板的两侧之间的导通中的信号传输的特征阻抗匹配，并且可以稳定可靠地安装半导体芯片。解决方案：在包括通过芯板上的电绝缘层形成的布线的多层布线板中，芯板包括多个通孔和由位于这些通孔中的导电材料组成的双面导通。双侧导通具有同轴结构，其包括中心线和围绕该中心线的同轴外围线，同轴外围线至少在圆周方向的一个位置具有凹口。此外，每个布线都布置在芯板上，用于将中心线与同轴外围线连接，并且用于与中心线连接的布线穿过存在凹口的区域。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2005167048A Multilayer wiring substrate 审中-公开
标题翻译：多层布线基板
公开(公告)号：JP2005167048A
公开(公告)日：2005-06-23
申请号：JP2003405464
申请日：2003-12-04
申请人： Dainippon Printing Co Ltd , 大日本印刷株式会社
发明人： YAMAGUCHI MASATAKA , KURAMOCHI SATORU
IPC分类号： H05K3/46 , H01L23/12
摘要： PROBLEM TO BE SOLVED: To provide a multilayer wiring substrate which is excellent in electrical property such as transmission property, corresponds to fining and narrow pitch, realizes insulation film formation method such as an electrodeposition method and reduces a manufacturing cost.
SOLUTION: In a core substrate and a multilayer wiring substrate which is formed by laminating a wiring layer and an insulating layer via an insulating layer on one or both surfaces of the core substrate, a core material used for the core substrate is silicon, the resistivity of the silicon is 10 Ωcm or more, and further preferably, the resistivity of the silicon is 10 Ωcm or more and 50 Ωcm or less.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了提供透光性等电性能优异的多层配线基板，相当于精细化和窄间距化，实现电沉积法等绝缘膜形成方法，降低制造成本。解决方案：在芯基板的一个或两个表面上通过绝缘层层叠布线层和绝缘层而形成的芯基板和多层布线基板中，用于芯基板的芯材为硅硅的电阻率为10Ωcm以上，进一步优选硅的电阻率为10Ωcm以上且50Ωcm以下。版权所有（C）2005，JPO＆NCIPI

6. 发明专利

JP2010025685A Method for manufacturing microchip 有权
标题翻译：制造MICROCHIP的方法
公开(公告)号：JP2010025685A
公开(公告)日：2010-02-04
申请号：JP2008185953
申请日：2008-07-17
申请人： Dainippon Printing Co Ltd , 大日本印刷株式会社
发明人： OZAWA YU , DAITO RYOICHI , FUJIMOTO KOJI , YAMAGUCHI MASATAKA
IPC分类号： G01N37/00 , B01J19/00 , B81C3/00 , C12M1/00 , H01L23/02
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing microchips allowing observation by transmitted light, and suppressing machining failure. SOLUTION: The microchip 10 includes a glass base material 11 for a through-hole, a main glass base material 12, and a silicon-including base material 20 interposed between the glass base material 11 for the through-hole and the main glass base material 12 and including a channel 21. When manufacturing the microchip 10, first of all, the main glass base material 12 and the silicon-including base material 20 are prepared, and anode joint of the silicon-including base material 20 to the main glass base material 12 is performed. Then, polishing is performed onto the silicon-including base material 20 on the main glass base material 12 to form a prescribed thickness of the silicon-including base material 20, and the channel 21 is formed on the silicon-including base material 20 by etching. Thereafter, the glass base material 11 for the through-hole is bonded onto the silicon-including base material 20 on which the channel 21 is formed. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造允许通过透射光观察并且抑制加工失败的微芯片的方法。解决方案：微芯片10包括用于通孔的玻璃基材11，主玻璃基材12和介于用于通孔的玻璃基材11和主要玻璃基材12之间的含硅基材20。玻璃基材12并且包括通道21.当制造微芯片10时，首先准备主玻璃基材12和含硅基材20，并且将含硅基材20的阳极接头连接到主玻璃基材12。然后，在主玻璃基材12上的含硅基材20上进行研磨，形成含硅基材20的规定厚度，通过蚀刻在含硅基材20上形成通道21 。此后，用于通孔的玻璃基材11被接合到其上形成有通道21的含硅基材20上。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2008041790A Manufacturing method of interposer board 有权
标题翻译：插座板的制造方法
公开(公告)号：JP2008041790A
公开(公告)日：2008-02-21
申请号：JP2006211674
申请日：2006-08-03
申请人： Dainippon Printing Co Ltd , 大日本印刷株式会社
发明人： YAMAGUCHI MASATAKA
IPC分类号： H01L23/32
摘要： PROBLEM TO BE SOLVED: To provide a method capable of manufacturing a very reliable interposer board in which the adhesion of a through-electrode to a wiring layer is excellent.
SOLUTION: The interposer board manufacturing method comprises processes of forming a wiring forming conductive material layer 18(19) on, at least, one surface of the board main body of a silicon board where the through electrode is provided penetrating it through in a perpendicular direction, and then patterning the wiring forming conductive material layer 18(19) into a wiring layer with an electrode pad electrically connected to the through electrode. In the interposer board manufacturing method, degassing holes 22 are bored in the wiring forming conductive material layer 18(19).
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够制造非常可靠的内插板的方法，其中贯通电极对布线层的粘合性优异。中间层制造方法包括在形成导电材料层18（19）的布线上形成布线的工艺，所述布线至少在其中穿过其中穿过的通孔的硅板的主板的至少一个表面上垂直方向，然后将形成导电材料层18（19）的布线图案化成具有与通孔电连接的电极焊盘的布线层。在插入板制造方法中，在形成导电材料层18（19）的布线中钻出脱气孔22。版权所有（C）2008，JPO＆INPIT

8. 发明专利

JP2004356160A Method of manufacturing wiring board 有权
公开(公告)号：JP2004356160A
公开(公告)日：2004-12-16
申请号：JP2003148812
申请日：2003-05-27
申请人： Dainippon Printing Co Ltd , 大日本印刷株式会社
发明人： AKAZAWA MIYUKI , KURAMOCHI SATORU , TAKANO ATSUSHI , NAKAYAMA KOICHI , YAMAGUCHI MASATAKA , MORI TOSHIAKI , FUKUOKA YOSHITAKA
IPC分类号： B26F1/28 , H01L23/12 , H05K3/40 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing wiring board by which a wiring board that is reduced in cross talk noise and provided with coaxial through holes capable of making impedance matching can be manufactured easily by securing high insulation reliability and connection reliability. SOLUTION: This method includes a step of coaxially forming a center fine hole 5 and external cylindrical holes 6 into a core substrate 2 by plasma etching from one surface of the substrate 2, a step of forming diffusion-of-conductive-substance preventing layers 7a and 7b and base conductive layers 8a and 8b on the internal wall surfaces of the holes 5 and 6, and a step of packing conductive substances 9a and 9b in the holes 5 and 6. The method also includes a step of forming a center through hole 5 and external through holes 6 by exposing the packed conductive substances 9a and 9b by polishing the surface of the substrate 2; a step of forming via holes connected to the conductive substance 9a packed in the center through hole 5 and, in addition, insulated from the conductive substance 9b packed in the external through holes 6 and, at the same time, forming wiring through an electrical insulating layer. COPYRIGHT: (C)2005,JPO&NCIPI

9. 发明专利

JP2004349603A Multilayer wiring board and its manufacturing method 有权
公开(公告)号：JP2004349603A
公开(公告)日：2004-12-09
申请号：JP2003147352
申请日：2003-05-26
申请人： Dainippon Printing Co Ltd , 大日本印刷株式会社
发明人： AKAZAWA MIYUKI , KURAMOCHI SATORU , TAKANO ATSUSHI , NAKAYAMA KOICHI , YAMAGUCHI MASATAKA , MORI TOSHIAKI , FUKUOKA YOSHITAKA
IPC分类号： H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a multilayer wiring board wherein the freedom of wiring design is high and a high density wiring is possible, and a manufacturing method of manufacturing such a multilayer wiring board readily. SOLUTION: In a multilayer wiring board with a wiring of two or more layers via an electric insulating layer on a core substrate, a core substrate having a plurality of through-holes which are filled with a conductive substance and are conductively connected in front-back sides is used. The opening diameter of the through-hole is in the range of 10 to 100 μm and a through-hole inner wall surface is provided with a conductive substance diffusion preventing layer. The wiring of a first layer formed on the core substrate via an electric insulating layer is connected to the conductive substance filled in the through-hole through a via. COPYRIGHT: (C)2005,JPO&NCIPI

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