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1. 发明专利

JP2009147948A High-speed serial data signal transmitter driver circuitry 审中-公开
标题翻译：高速串行数据信号发射机驱动电路
公开(公告)号：JP2009147948A
公开(公告)日：2009-07-02
申请号：JP2008320310
申请日：2008-12-16
申请人： Altera Corp , アルテラコーポレイションAltera Corporation
发明人： WONG WILSON , CHAN ALLEN , SHUMARAYEV SERGEY , DING WEIQI
IPC分类号： H03K19/0175 , H04L25/02
CPC分类号： H04L25/028
摘要： PROBLEM TO BE SOLVED: To provide high-speed serial digital data signal transmitter driver circuitry.
SOLUTION: The present invention relates to transmitter driver circuitry for outputting a high-speed serial data signal having a serial bit rate in the range of about 10 Gbps, including H-tree driver circuitry having only a main driver stage and a post-tap driver stage. At least one transistor forming a portion of the H-tree driver circuitry further provides electrostatic discharge protection for the circuitry.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供高速串行数字数据信号发射器驱动电路。解决方案：本发明涉及用于输出具有约10Gbps范围内的串行比特率的高速串行数据信号的发射机驱动器电路，包括仅具有主驱动级和后级的H树驱动器电路 tap驱动阶段。形成H树驱动器电路的一部分的至少一个晶体管进一步为电路提供静电放电保护。版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2008072716A Digital adaptation circuitry and method for programmable logic devices 审中-公开
标题翻译：数字适应电路和可编程逻辑器件的方法
公开(公告)号：JP2008072716A
公开(公告)日：2008-03-27
申请号：JP2007237202
申请日：2007-09-12
申请人： Altera Corp , アルテラコーポレイションAltera Corporation
发明人： WONG WILSON , CHAN DORIS PO CHING , SHUMARAYEV SERGEY , MAANGAT SIMARDEEP , HOANG TIM TRI , LAI TIN H , TRAN THUNGOC M
IPC分类号： H04B3/14 , H04B3/06 , H04L25/03
CPC分类号： H04L25/03885
摘要： PROBLEM TO BE SOLVED: To provide digital adaptation circuitry and method for programmable logic devices.
SOLUTION: This method provides for controlling equalization of an incoming data signal. The method includes detecting two successive differently valued bits in the data signal, determining whether transition in the incoming data signal between those bits occurs relatively late or relatively early, and increasing the equalization of the incoming data signal if it is relatively late.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为可编程逻辑器件提供数字适配电路和方法。解决方案：该方法用于控制输入数据信号的均衡。该方法包括检测数据信号中的两个连续的不同值的位，确定这些位之间的输入数据信号中的转换是否相对较晚或相对较早地发生，如果相对较晚，则增加输入数据信号的均衡。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2006287964A Interconnection and input/output resources for programmable logic integrated circuit devices 有权
标题翻译：用于可编程逻辑集成电路设备的互连和输入/输出资源
公开(公告)号：JP2006287964A
公开(公告)日：2006-10-19
申请号：JP2006146009
申请日：2006-05-25
申请人： Altera Corp , アルテラコーポレイションAltera Corporation
发明人： NGAI TONY , PEDERSEN BRUCE , SHUMARAYEV SERGEY , SCHLEICHER JAMES , HUANG WEI-JEN , HUTTON MICHAEL , MARURI VICTOR , PATEL RAKESH , KAZARIAN PETER J , LEAVER ANDREW , MENDEL DAVID W , PARK JIM
IPC分类号： H03K19/177 , H01L21/82 , H03K19/173
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/17728 , H03K19/17744
摘要： PROBLEM TO BE SOLVED: To provide interconnection resources to be applied to a programmable logic device for accelerating an operating speed of a programmable logic array integrated circuit. SOLUTION: A programmable logic integrated circuit device (10) has a plurality of regions (20) of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors) are provided for making programmable interconnection to, from and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources (200a, 210a, 230a) may have what may be termed normal signal speed, while a smaller minor portion (200b, 210b, 230b) may have significantly faster signal speed. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供应用于可编程逻辑器件的互连资源，以加速可编程逻辑阵列集成电路的工作速度。解决方案：可编程逻辑集成电路器件（10）具有多个可编程逻辑区域（20），该可编程逻辑区域设置在该区域的多个相交行和列中的该器件上。互连资源（例如，互连导体）被提供用于对区域之间进行可编程的互连。这些互连资源中的至少一些以架构上相似但具有显着不同的信号传播速度特性的两种形式提供。例如，这种双形互连资源（200a，210a，230a）的主要或更大部分可以具有所谓的正常信号速度，而较小次要部分（200b，210b，230b）可具有明显更快的信号速度。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2012130047A Programmable receiver equalization circuit and method 有权
标题翻译：可编程接收器均衡电路和方法
公开(公告)号：JP2012130047A
公开(公告)日：2012-07-05
申请号：JP2012022868
申请日：2012-02-06
申请人： Altera Corp , アルテラコーポレイションAltera Corporation
发明人： MAANGAT SIMARDEEP , SHUMARAYEV SERGEY , WONG WILSON , TU NGOC TRAN
IPC分类号： H04B3/04 , H04L25/02 , H04L25/03
CPC分类号： H04L25/03885 , H04B3/04 , H04L25/03019
摘要： PROBLEM TO BE SOLVED: To provide an equalization circuit for appropriately compensating for attenuation caused by transmission media.SOLUTION: Data signals transmitted over transmission media suffer from attenuation caused by the transmission media. An equalization circuit (106) includes a plurality of stages (202) arranged in series to allow frequency responses of the stages (202) to be integrated together. Each stage (202) is programmable to insert a zero, thus causing the frequency response of the stage (202) to be increased in magnitude by 20 dB/decade. The frequency location of zero is also programmable to allow each stage (202) to contribute to a certain amount of a gain for a specific frequency. Each stage (202) is also programmable to determine the location of a pole for the reduction of high frequency noise and cross-talk cancellation.
摘要翻译：要解决的问题：提供用于适当地补偿由传输介质引起的衰减的均衡电路。解决方案：通过传输介质传输的数据信号受到传输介质所造成的衰减。均衡电路（106）包括串联布置的多个级（202），以允许级（202）的频率响应被集成在一起。每个级（202）可编程为插入零，从而使得级（202）的频率响应在幅度上增加20dB /十倍。零的频率位置也是可编程的，以允许每个级（202）为特定频率贡献一定量的增益。每个级（202）也是可编程的，以确定用于降低高频噪声和串扰消除的极点的位置。版权所有（C）2012，JPO＆INPIT

5. 发明专利

JP2007028625A Programmable receiver equalization circuit and method 有权
标题翻译：可编程接收器均衡电路和方法
公开(公告)号：JP2007028625A
公开(公告)日：2007-02-01
申请号：JP2006193262
申请日：2006-07-13
申请人： Altera Corp , アルテラコーポレイションAltera Corporation
发明人： MAANGAT SIMARDEEP , SHUMARAYEV SERGEY , WONG WILSON , TRAN THUNGOC
IPC分类号： H04B3/04 , H04L25/03
CPC分类号： H04L25/03885 , H04B3/04 , H04L25/03019
摘要： PROBLEM TO BE SOLVED: To provide an equalization circuit for appropriately compensating for attenuation caused by transmission media.
SOLUTION: Data signals transmitted over transmission media suffer from attenuation caused by the transmission media. Equalization circuitry (106) may include a plurality of stages (202) arranged in series to allow frequency responses of the stages (202) to be aggregated together. Each stage (202) may be programmable to insert a zero, thus causing the frequency response of the stage (202) to be increased in magnitude by 20 dB/decade. The frequency location of zero may also be programmable to allow each stage (202) to contribute to a certain amount of a gain for a specific frequency. Each stage (202) may also be programmable to determine the location of a pole for the reduction of high frequency noise and cross-talk cancellation.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供用于适当地补偿由传输介质引起的衰减的均衡电路。解决方案：通过传输介质传输的数据信号受到传输介质所造成的衰减。均衡电路（106）可以包括串联布置的多个级（202），以允许级（202）的频率响应聚合在一起。每个级（202）可以是可编程的以插入零，从而使得级（202）的频率响应在幅度上增加20dB /十倍。零的频率位置也可以是可编程的，以允许每个级（202）为特定频率贡献一定量的增益。每个级（202）也可以被编程以确定用于降低高频噪声和串扰消除的极点的位置。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2013251916A High-speed serial data signal receiver circuitry 有权
标题翻译：高速串行数据信号接收电路
公开(公告)号：JP2013251916A
公开(公告)日：2013-12-12
申请号：JP2013161153
申请日：2013-08-02
申请人： Altera Corp , アルテラコーポレイションAltera Corporation
发明人： DING WEIQI , LIU MENGCHI , WONG WILSON , SHUMARAYEV SERGEY
IPC分类号： H04L25/03 , H04B3/04
CPC分类号： H04L25/03878 , H04L7/0054
摘要： PROBLEM TO BE SOLVED: To provide preferable and efficient data conversion processes between a high-speed serial data format and a parallel data format.SOLUTION: Receiver circuitry for receiving a high-speed serial data signal having a serial bit rate in the range of about 10 Gbps includes a two-stage continuous-time linear equalizer having only two stages connected in series. Each of the stages has a DC gain parameter which is variable, and a pole and/or a zero whose locations are variable in terms of the frequency. The DC gain parameter and the pole and/or zero locations of each stage are variable by programs.
摘要翻译：要解决的问题：提供高速串行数据格式和并行数据格式之间优选和有效的数据转换处理。解决方案：接收电路，用于接收串行比特率在大约的范围内的高速串行数据信号 10Gbps包括仅具有串联连接的两级的两级连续时间线性均衡器。每个级具有可变的DC增益参数，以及位置在频率方面可变的极点和/或零点。每个阶段的直流增益参数和极点和/或零点位置都可以通过程序进行变化。

7. 发明专利

JP2011103678A Digital adaptation circuitry and method for programmable logic device 有权
标题翻译：数字适配电路和可编程逻辑器件的方法
公开(公告)号：JP2011103678A
公开(公告)日：2011-05-26
申请号：JP2010291281
申请日：2010-12-27
申请人： Altera Corp , アルテラコーポレイションAltera Corporation
发明人： WONG WILSON , CHAN DORIS PO CHING , SHUMARAYEV SERGEY , MAANGAT SIMARDEEP , HOANG TIM TRI , LAI TIN H , TRAN THUNGOC M
IPC分类号： H04B3/04 , H04L25/03
CPC分类号： H04L25/03885
摘要： PROBLEM TO BE SOLVED: To provide a digital adaptation circuitry and method for a programmable logic device. SOLUTION: A method of controlling equalization of an incoming data signal includes: detecting two continuous bits having different values in the data signal; determining whether transition in the incoming data signal between the two bits is relatively slow or relatively fast; and increasing the equalization of the incoming data signal when the transition is relatively slow. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为可编程逻辑器件提供数字适配电路和方法。控制输入数据信号的均衡的方法包括：检测数据信号中具有不同值的两个连续位; 确定两个位之间的输入数据信号中的转换是相对较慢还是相对较快; 并且当转换相对较慢时，增加输入数据信号的均衡。版权所有（C）2011，JPO＆INPIT

8. 发明专利

JP2010098746A Signal adjustment receiver circuitry 有权
标题翻译：信号调整接收机电路
公开(公告)号：JP2010098746A
公开(公告)日：2010-04-30
申请号：JP2009269334
申请日：2009-11-26
申请人： Altera Corp , アルテラコーポレイションAltera Corporation
发明人： WONG WILSON , RAKESH PATEL H , SHUMARAYEV SERGEY , LAI TIN H
IPC分类号： H04B3/04 , H03K19/0175 , H03K19/094 , H03K19/0952 , H04L25/03
CPC分类号： H04B7/005 , H04L25/03006 , H04L25/061
摘要： PROBLEM TO BE SOLVED: To provide a technology for adjusting a digital signal received from a communication path.
SOLUTION: Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver receives a signal from a communication path which attenuates at least some frequency components of the signal. The receiver includes an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies but not for low frequencies. For low frequency adjustment, the control block controls the normalized signal amplitude in the signal normalization block. In this manner, controlled adjustment for low frequency content is performed in the signal normalization block.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于调整从通信路径接收的数字信号的技术。公开了用于调整从通信路径接收的信号的系统和方法。接收机从通信路径接收信号，该信号衰减信号的至少一些频率分量。接收机包括调整接收信号的频率内容中的至少一些的均衡块，提供归一化信号幅度和/或归一化边沿斜率的信号归一化块以及控制块。在一个实施例中，控制块控制用于高频而不是低频的均衡块中的频率调整。对于低频调整，控制块控制信号归一化块中的归一化信号幅度。以这种方式，在信号归一化块中执行低频内容的受控调整。版权所有（C）2010，JPO＆INPIT

9. 发明专利

JP2009153132A Transceiver system having reduced latency uncertainty 审中-公开
标题翻译：收缩系统具有减少的延迟不确定性
公开(公告)号：JP2009153132A
公开(公告)日：2009-07-09
申请号：JP2008322994
申请日：2008-12-18
申请人： Altera Corp , アルテラコーポレイションAltera Corporation
发明人： CARVALHO NEVILLE , DAVIDSON ALLAN THOMAS , TURUDIC ANDY , PEDERSEN BRUCE B , MENDEL DAVID W , KANKIPATI KALYAN , ZHENG MICHAEL MENGHUI , SHUMARAYEV SERGEY , PARK SEUNGMYON , HOANG TIM TRI , THARMALINGAM KUMARA
IPC分类号： H04L7/033 , H03K19/173 , H03L7/08 , H04L13/08
CPC分类号： H04L25/14
摘要： PROBLEM TO BE SOLVED: To provide a transceiver system having a reduced latency uncertainty. SOLUTION: The transceiver system has a word aligner with a latency uncertainty of zero. The system also has a bit slipper coupled with the word aligner. The bit slipper slips bits in such a manner that a total delay caused by word alignment of the word aligner and by a bit slip of the bit slipper is constant with respect to all phases of a recovery clock. COPYRIGHT: (C)2009,JPO&INPIT

10. 发明专利

JP2009065694A Interconnection and input/output resources for programmable logic integrated circuit devices 有权
标题翻译：用于可编程逻辑集成电路设备的互连和输入/输出资源
公开(公告)号：JP2009065694A
公开(公告)日：2009-03-26
申请号：JP2008270378
申请日：2008-10-20
申请人： Altera Corp , アルテラコーポレイションAltera Corporation
发明人： NGAI TONY , PEDERSEN BRUCE , SHUMARAYEV SERGEY , SCHLEICHER JAMES , HUANG WEI-JEN , HUTTON MICHAEL , MARURI VICTOR , PATEL RAKESH , KAZARIAN PETER J , LEAVER ANDREW , MENDEL DAVID W , PARK JIM
IPC分类号： H03K19/173 , H01L21/82 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/17728 , H03K19/17744
摘要： PROBLEM TO BE SOLVED: To provide interconnection resources applied to programmable logic devices for accelerating an operating speed of a programmable logic array integrated circuit device. SOLUTION: A programmable logic integrated circuit (10) has a plurality of regions of programmable logic (20) disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, etc.) are provided for making programmable interconnections to, from and/or between the regions. At least some of these interconnection resources are provided in two forms having architecturally similar but significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources (200a, 210a, 230a) may have what may be termed normal signal speed, while a smaller minor portion (200b, 210b, 230b) may have significantly faster signal speed. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供应用于可编程逻辑器件的互连资源，以加速可编程逻辑阵列集成电路器件的工作速度。解决方案：可编程逻辑集成电路（10）具有多个可编程逻辑区域（20），该多个可编程逻辑区域设置在该区域的多个相交行和列的多个设备上。提供互连资源（例如，互连导体等），用于对区域之间和/或之间进行可编程互连。这些互连资源中的至少一些以具有架构上相似但显着不同的信号传播速度特性的两种形式提供。例如，这种双形互连资源（200a，210a，230a）的主要或更大部分可以具有所谓的正常信号速度，而较小次要部分（200b，210b，230b）可具有明显更快的信号速度。版权所有（C）2009，JPO＆INPIT

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